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MSP430 BSL "TEST" pin

Jamie Maxwell
Expert 1530 points

Other Parts Discussed in Thread: MSP430F2122

I have read through App note SLAU319A and describes how to enter the BSL using RESET and TEST pins (devices with TEST pin).

It states that: "If the second rising edge at the TEST pin is applied while RST/NMI is still low, the TEST signal is kept low internally (application mode)." Does this mean the pin is internally pulled low by HW?

I am looking to connect the test pin to a different pin when in Normal mode and I want to know if the "TEST" pin is pulled down or if it can be set to high Z input (or disconnected)

There is also a note that during normal operation the TEST pin is logic 0. If it's internally low, then do I am guessing I do not need external HW to pull low. Will there be any ill-effects if I am toggleing this pin during normal operation?

It also says that TCK must not be connected. Why? is this only during program mode? does it need to be left floating?

Thanks

J

  • 0
    Guru 227245 points

    Jmax604 said:
    Does this mean the pin is internally pulled low by HW?

    No. The internal signal that is normally read from the pin is kept low (latched). The pin itself is not pulled, at least AFAIK.

    Jmax604 said:
    I want to know if the "TEST" pin is pulled down or if it can be set to high Z input (or disconnected)

    You cannto 'set' the TEST pin. It is a plain input.

    However, the details of the TEST pin differ a bit with the actual MSP. Some have additional SBW functionality (a serialized JTAG) on this pin, others do not have a TEST pin at all.

  • 0 in reply to Jens-Michael Gross
    Expert 1530 points

     

    I am working with the MSP430F2122 which has multiplexed JTAG pins.

    I am trying to find out if it safe to connect this line directly with the I2C_Data line (i.e. tie them together)

     

    The App note on JTAG (SLAU320B) says:

    MSP430 devices with Spy-Bi-Wire (SBW) access:

    The SBW interface and any access to the JTAG interface is disabled while the TEST/SBWTCK pin is

    held low. This is accomplished by an internal pulldown resistor. The pin can also be tied low externally.

    This description sounds like the pin is pulled low and therefore the I2C line would also be pulled low.

    But the App note on the BootStrap Loader (SLAU319A)says:

    If the second rising edge at the TEST pin is applied while RST/NMI is still low, the

    TEST signal is kept low internally (application mode).

    Jens-Michael Gross said:
     
    Does this mean the pin is internally pulled low by HW?
    No. The internal signal that is normally read from the pin is kept low (latched). The pin itself is not pulled, at least AFAIK.

    [/quote]

    The App note on JTAG (SLAU320B) also reads:

    The TEST input exists only on MSP430 devices with shared JTAG function, usually assigned to port 1. To enable these pins for JTAG communication, a logic level 1 must be applied to the TEST pin. For normal operation (non-JTAG mode), this pin is internally pulled down to ground, enabling the shared pins as standard port I/O.

     

     

    Would this mean that a logic one on the TEST pin during normal appication mode will cause the shard JTAG ports (P1.4-P1.7) to switch from GPIO to JTAG mode pins?

    This is not clear to me.

    Is there anyone who knows about the architecture or the operation of the TEST pin on this device?

     

    The host will have full control of this pin, so when we enter the BSL, pin12 (I2C_Data) can be ignored. What I am concerned about is what will happen when the device is in ‘normal’ mode.

    Will the TEST pin pull I2C_data low? 

    Will there be any ill-effects as the TEST pin is toggling as data is transferred over I2C.

     

    There is also the question about TCK. It says that this pin must not be connected. Does this mean it must be ‘floating’ while in BSL mode?

    Thanks

     

  • 0 in reply to Jamie Maxwell
    Guru 58965 points

    For BSL, the BSL hardware interface must drive TEST pin in the way conforming to the BSL entry sequence.

    For 4-wire JTAG operation, the JTAG hardware interface must drive TEST pin high.

    For SBW operation, the SBW hardware interface must drive TEST pin as the SBWTCK.

    For normal operation (that is, none of the above), TEST pin may be left unconnected . Driving it low is okay but unnecessary (there is an internal pull-down). If P1.4, 5, 6, and 7 are all unused, driving TEST pin high is okay too.

  • 0 in reply to old_cow_yellow
    Expert 1530 points

    old_cow_yellow said:

     If P1.4, 5, 6, and 7 are all unused, driving TEST pin high is okay too.

    So if I want to use P1.4 - 1.7 as GPIO in normal operation then I cannot drive TEST high (toggle)..... Correct?

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