MSP430FR2476: RTC doesn't work with ACLK Clock source

Hello Pavel,

This seems a bit odd.  Does the FR2476 demonstrate this problem running in debug mode and normal operating mode?

I patched a copy of msp430fr267x_RTC_03.c with a fragment from msp430fr267x_CS_04.c and ran it successfully on a Launchpad. (RTC_03 claims to use XT1 but doesn't). I wonder if we're doing something differently.

msp430fr267x_RTC_03.c:

https://dev.ti.com/tirex/explore/node?node=A__AKNf3in9mWWJ84fcO5LnGA__msp430ware__IOGqZri__LATEST

msp430fr267x_CS_04.c:

https://dev.ti.com/tirex/explore/node?node=A__AJBq58I7kSozvrhJisyDxQ__msp430ware__IOGqZri__LATEST

//******************************************************************************
//  MSP430FR267x Demo -  RTC, using ACLK as clock source, toggle P1.0 every 1s
//
//  Description: Configure ACLK to use REFO as RTC source clock,
//               ACLK = REFO = 32kHz, MCLK = SMCLK = default DCODIV = ~1MHz.
//
//   ACLK = XT1 = 32kHz, MCLK = SMCLK = default DCODIV = ~1MHz.
//
//           MSP430FR2676
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST            |
//        |               |
//        |               |
//        |          P1.0 |---> LED
//        |               |
//
//   Longyu Fang
//   Texas Instruments Inc.
//   August 2018
//   Built with IAR Embedded Workbench v7.12.1 & Code Composer Studio v8.1.0
//******************************************************************************
#include <msp430.h>
#define USE_XT1 1
int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;               // Stop watchdog timer

    P1OUT &= ~BIT0;                         // Clear P1.0 output latch for a defined power-on state
    P1DIR |= BIT0;                          // Set P1.0 to output direction

    PM5CTL0 &= ~LOCKLPM5;                   // Disable the GPIO power-on default high-impedance mode
                                            // to activate previously configured port settings
#if USE_XT1
    P2SEL0 |= BIT0 | BIT1;                  // P2.0~P2.1: crystal pins
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);      // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    }while (SFRIFG1 & OFIFG);               // Test oscillator fault flag
    CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;  // set ACLK = XT1CLK = 32768Hz
#endif // USE_XT1

    // RTC count re-load compare value at 32.
    // 1024/32768 * 32 = 1 sec.
    RTCMOD = 32-1;
                                            // Initialize RTC
    // Source = ACLK = REFO, divided by 1024
    SYSCFG2 |= RTCCKSEL;                    // Select ACLK as RTC clock
    RTCCTL = RTCSS_1 | RTCSR | RTCPS__1024 | RTCIE;

    __bis_SR_register(LPM3_bits | GIE);     // Enter LPM3, enable interrupt
}

// RTC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=RTC_VECTOR
__interrupt void RTC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(RTCIV,RTCIV_RTCIF))
    {
        case  RTCIV_NONE:   break;          // No interrupt
        case  RTCIV_RTCIF:                  // RTC Overflow
            P1OUT ^= BIT0;
            break;
        default: break;
    }
}

Thank you Bruce.

Pavel, do you have your project running now?

Hello Bruce, Hello Dennis,

I have been testing for two days on the Stater Kit with MSP430FR2476 and found out that the problem appears in both debug mode and normal operating mode depending on how the FW comes into the MCU, power cycle and reset. Sometimes it appears only during a debug session under JTAG, sometimes after "Load" from CCS. The Reset button can help but not always. After full power cycle the FW works. 

I was sequentially reducing my code approaching to yours and managed to find the code line causing this problem:

CSCTL5 |= SMCLKOFF_1;

if it is placed between the line 42 and 47 the problem appears regularly after "Load" and Debug mode with JTAG. The Reset button doesn't help. Only unplugging the Starter Kit from the USB and plugging it again lets FW working. But after Reset it stops working again. 

One thing more. In your code example the XT1 amplifier doesn't run while the RTC is running. Activating the XT1 amplifier, re-configuring the FLL to 16MHz makes the problem more difficult to reproduce. It starts to depend on delays of the XT1 amplifier or startup time of the Clock Generator in our HW. I also managed to reproduce this problem adding delay between CSCTL5 |= SMCLKOFF_1 and entering in the LPM3.

Best regards,

Pavel

I just tripped over Erratum RTC15 for the FR2111 [Ref Errata Sheet (SLAZ687Q) p. 12], which describes an RTC inability to switch clocks if its current clock (XT1 in that case) is stopped. It's a different device, and the particulars are different, but it sounds like something that the FR2-series RTC is susceptible to.

Thank you. Yes, I think so.

I had tested the RTC with this case before. If XT1CLK is used as the clock source for the RTC Counter and XT1CLK stops, switching the RTC to the VLO Clock works good. I had implemented this as a workaround to our problem with the RTC before you found out your workaround. 

Thank you very much for explanation and the workaround. It seems to works properly. I was unable to provoke the error.