MSP430FR2475: 6-pin behavior after releasing reset

Hi,

It seems this is not related to FR2475, because P1.6's voltage is pulled up 80us earlier than reset. (time: 200us/div, visual calculated result, please refer to the actual calculation).

Please check the circuit schematic and PCB at the same time.

Regards,

Helic

Hi Helic-san,

Customer has question as follows. Would you answer it, please?
1. During device reset state, the software is not running, correct? And also GPIO cannot control?
2. Regarding 6pin, this pin is pulled-up while device is in reset state?

Best Regards,
Fujiwara

Hi, Yasushi

Yasushi Fujiwara said:

1. During device reset state, the software is not running, correct? And also GPIO cannot control?

Software is not running, GPIO is in default status.

In MSP430FR2475 User's Guide 8.3.1 Configuration After Reset:

        After a BOR reset, all port pins are high-impedance with Schmitt triggers and their module functions
        disabled to prevent any cross currents.

Yasushi Fujiwara said:

2. Regarding 6pin, this pin is pulled-up while device is in reset state?

Yes, I think P1.6 is pullup by external signal. Because while Reset = 0, the device is in reset stage. But P1.6 is pullup before Reset = 1.

Regards,

Helic

Hi Helic,

What customer want to do is send test and RST signals to the MSP430 from an external MPU to put the MSP430 in BSL mode.
The following sequence of signals is sent from an external MPU.


However, after the second high output of test signal, a high signal is output from port 1.6 pin, and the BSL mode is not entered in our current circuit configuration. Also, this 1.6 pin does not have an external pull-up circuit configuration.


[Question]
Now that we've reviewed the MSP430 datasheet, there's something to be curious about. When the test signal goes high, the JTAG function inside MSP is activated and the 1.6 pin is pulled up internally. Is customer understanding correct?




Best Regards,
Fujiwara

Hello Experts,

Would you answer above question, please? Customer is waiting your answer.

Best Regards,
Fujiwara

Hello Experts,

Would you answer above question, please? Customer is waiting your answer.

Best Regards,
Fujiwara

Hello Experts,

Would you respond to question, please? Customer is waiting your answer.

Best Regards,
Fujiwara

Hi, Yasushi

Sorry for my late.

I didn't receive this thread's E2E e-mail notification in the few past days.

I will look into this question again~

Yasushi Fujiwara said:

[Question]
Now that we've reviewed the MSP430 datasheet, there's something to be curious about. When the test signal goes high, the JTAG function inside MSP is activated and the 1.6 pin is pulled up internally. Is customer understanding correct?

Bootloader starts at the falling edge of Test signal. But if BSL is disabled, the bootloader sequence will let device entering JTAG mode. (In the figure you send 2.3 memory programming control sequence Case 2b.).

TCLK and P1.6 are the same pin, but I still don't think this is normal.

---

Can customer do some test on MSP430 without external circuit to confirm this is MSP430's internal issue?

Regards,

Helic

Hello Helic,

Customer did the test without the external circuit and confirmed same phenomenon. Please see below. Would you verify this phenomenon, please?


Best Regards,
Fujiwara

Hi, Yasushi

What's the image customer flash to this device?

I recommend that customers erase the chip program and test it again.

If this P1.6 is still set during the set of Test signal, it can be confirmed that this is abnormal.

Another question: can customer enter BSL now in this condition?

Regards,

Helic

Hi Helic,

Customer would like to know whether Port1.6 will be pulled up when test signal is input due to JTAG operated. Would you answer it, please?

Best Regards,
Fujiwara

Hi, Yasushi

1. Have customers tested on the chip without programs (empty chip)? I mentioned above.

2. How many chips has this issue? How many chips have customer tested? What's the test results?

3. If there is still a problem, I will test it simultaneously in the TI lab. I will try to reproduce this P1.6 pulled-up phenomenon.

Yasushi Fujiwara said:

whether Port1.6 will be pulled up when test signal is input due to JTAG operated

I need to test, but I think this is abnormal.

Regards,

Helic

Hi Helic,

Customer confirmed your question.
1. Customer verified using evaluation board LP MSP430FR2476.
The P1.6 port goes low/high in sync with the test signal. It seems to respond to the second high test signal. The following figure shows the observed waveform. Please verify this phenomenon.


2. Customer has checked this phenomenon by;
- one EVM
- two customer board

[Question]
Customer would like to know a specifications of the MSP430 microcontroller.
In the block diagram below, what is the specification for the from JTAG (red mark) route to control Pullup/Pulldown?

Hi, Yasushi

Add Gary to support BSL question.

Helic

Hi Team,

Do you have any update? Customer is waiting your answer.

Best Regards,
Fujiwara

Hi Yasushi,

I also see this phenomenon and need to check with design about it.

Hi Gary,

Do you have ant update? Customer is waiting your comment.

Best Regards,
Fujiwara

The design team are looking into this case now but still no feedback to me, I will send a push email to them. Sorry about that.

HI,

Do you have update? It was already passed 10 days...

Best Regards,
Fujiwara

Hi 

I have pushed our design team yesterday and they are working to setup the data base for it now. Due to most of the design resources are working on MSPM0 new device development so it is limited for the debug for MSP430 device please give us some time for it. Thanks.

Hi,

Do you have any update on this? Customer is waiting TI comments. Customer should be fixed as soon as possible. Please help to answer the question and fix it as soon as possible.

Best Regards,
Fujiwara

Hi Fujiwara,

I got the feed back from our design team as below last week

Design team are trying to check the design if they can find the signature of the issue. Also DV team is trying to setup the simulation for this project with the problem scenario.

I will feed back to you when our design team get any feedback to me, or you can send me the email (garygao@ti.com),we can discuss it offline.

Hi,

I glad to hear that design team will do the simulation. Please keep update on this thread.

Best Regards,
Fujiwara

Hi,

Do you have any update?

Best Regards,
Fujiwara