Other Parts Discussed in Thread: MSP430WARE, , MSP-EXP430FR5969
I am having a problem with the SPI CLK output for the eSCU_A1 module. Since my code wasn't working, I pulled the TI example for the eSCU_A0 module example code for a 3-SPI Master and modified it for the eSCU_A1 module. Unfortunately, that code doesn't work either. I have put an oscilloscope on the SPI pins
A1 SPI CLK -> (Expected = Clock, Measured = noise, no clk)
A1 SPI SIMO -> (Expected = Data packets, Measured = Data packets)
A1 SPI SOMI -> No Driver (Expected value = noise, Measured = noise)
Here is the test code. I have searched the forums and cannot find a similar problem with a solution that worked for me. Any ideas?
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//******************************************************************************
// MSP430F59xx Demo - eUSCI_A1, SPI 3-Wire Master Incremented Data
//
// Description: SPI master talks to SPI slave using 3-wire mode. Incrementing
// data is sent by the master starting at 0x01. Received data is expected to
// be same as the previous transmission TXData = RXData-1.
// USCI RX ISR is used to handle communication with the CPU, normally in LPM0.
// ACLK = 32.768kHz, MCLK = SMCLK = DCO ~1MHz. BRCLK = ACLK/2
//
//
// MSP430FR5969
// -----------------
// /|\ | |
// | | |
// ---|RST |
// | |
// | P2.5|-> Data Out (UCA1SIMO)
// | |
// | P2.6|<- Data In (UCA1SOMI)
// | |
// | P2.4|-> Serial Clock Out (UCA1CLK)
//
//******************************************************************************
#include <msp430.h>
volatile unsigned char RXData = 0;
volatile unsigned char TXData;
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
// Configure GPIO
P2SEL1 |= BIT4 | BIT5 | BIT6; // USCI_A1 operation
// P2SEL0 &= ~(BIT4 | BIT5 | BIT6);
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
// Configure USCI_A1 for SPI operation
UCA1CTLW0 = UCSWRST; // **Put state machine in reset**
UCA1CTLW0 |= UCMST | UCSYNC | UCCKPL | UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA1CTLW0 |= UCSSEL__SMCLK; // SMCLK
UCA1BR0 = 0x02; // /2
UCA1BR1 = 0; //
UCA1MCTLW = 0; // No modulation
UCA1CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCA1IE |= UCRXIE; // Enable USCI_A1 RX interrupt
TXData = 0x1; // Holds TX data
while(1)
{
UCA1IE |= UCTXIE;
__bis_SR_register(LPM0_bits | GIE); // CPU off, enable interrupts
__delay_cycles(2000); // Delay before next transmission
TXData++; // Increment transmit data
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A1_VECTOR))) USCI_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA1IV, USCI_SPI_UCTXIFG))
{
case USCI_NONE: break;
case USCI_SPI_UCRXIFG:
RXData = UCA1RXBUF;
UCA1IFG &= ~UCRXIFG;
__bic_SR_register_on_exit(LPM0_bits); // Wake up to setup next TX
break;
case USCI_SPI_UCTXIFG:
UCA1TXBUF = TXData; // Transmit characters
UCA1IE &= ~UCTXIE;
break;
default: break;
}
}
