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MSP430FR2355: PWM Jitter(100% duty) randomly in MSP430

Sivarajan Ramachandran
Prodigy 20 points

Part Number: MSP430FR2355

Hi,

  I am using msp430fr2355 with following setup. Using 2 pwms . One of them after some time opens 100% duty and causes jitter(as shown in attached waveform.

void pwm_init(void)
{

PM5CTL0 &= ~LOCKLPM5;

TB1CCR0 = 400-1; // PWM Period
TB1CCTL1 = OUTMOD_7;// | CCIE; // CCR1 reset/set
TB1CTL = TBSSEL__SMCLK | MC__UP | TBCLR; // | TBIE; // SMCLK, up mode, clear TBR
_delay_cycles (180); 
TB3CCR0 = 400-1; // PWM Period
TB3CCTL5 = OUTMOD_7;

TB3CTL = TBSSEL__SMCLK | MC__UP | TBCLR;

}

Please help resolve this issue.

Thanks,

Sivarajan

  • 0
    Guru 102905 points

    The scope traces shows no obvious jitter, though I do see a missing pulse in the lower trace.

    The code you posted sets the duty cycle to 0%, so I expect there's other code that sets TB1CCR1 and TB3CCR5. What does that look like?

    [Edit: Also, I see that the FR2355 is affected by Erratum TB25 [Ref Errata Sheet (SLAZ695J) p. 11], so you need to not depend on CLLD.]

  • 0 in reply to Bruce McKenney
    Prodigy 20 points

    Thanks for the reply, by jitter i mean the duty cycle of lower trace is 100% randomly.

    The other code loads CCR register as follows

    //#define DUTY TB1CCR1 
    //#define DUTY1 TB3CCR5 

    DUTY = DUTY1 = duty; 

    In Errata it says

    "In up mode, TBxCCRn value is immediately transferred to TBxCLn when TBxCCTLn.CLLD bits are set or 0x01 or 0x10"

    In my Initialization code i have not set CLLD, and remains at default 0x00.

    so question is will it still affect the PWM?,

    i will try loading the CCR through timer overflow ISR anyway and share result.

    Thanks Again..

  • 0 in reply to Sivarajan Ramachandran
    TI__Genius 14880 points

    Hello Sivarajan,

    After you got the latest results, you can set a new post and our American colleague will respond to you in 24 hours because the next few days are Chinese Qingming Festival and I will be back to office on 14th April.

    Best Regards,

    Janz Bai

  • 0 in reply to Sivarajan Ramachandran
    Guru 102905 points

    The Erratum only applies to CLLD=1 or =2, so if you don't set it (CLLD=0) it doesn't affect you. But CLLD=1 or =2 are (to my mind) the only useful settings, so in effect there is no CLLD feature.

    Setting the CCRn in the overflow (TBIFG) or CCR0 (CCTL0:CCIFG) ISR is usually a good bet. There are some cases where setting it in the CCRn ISR works better.

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