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MSP430F5529: How to make ADC12 sample synchronous to Timer B interrupt

David Summers
Intellectual 475 points
Part Number: MSP430F5529


Feel sure this must be possible, but haven't yet found how route the signal.

Here is what I have, a PWM is running on Timer B0 - it has a duty period of about 1200 cycles of SMCLK, that is the clock I'm using for Timer B0.

Now I want a couple of ADC measurements to be taken, synchronous to the PMW period. I can clock ADC12 to SMCLK  - and thats good. But really what I want is  Sequence of Channels conversion is started with same timing as the PWM.

So either that the interrupt on Timer B, starts the ADC12 sequence. Or that the interrupt routine that handles Timer B, can take an action that starts the ADC12 sequence.

I can see I could toggle ADC12ENC to stop the ADC, and only having it run with the PWM Period - but that seems a cludge - but can't see any other trigger I can control.

So what are peoples thoughts? Am I missing something, Or do i have to set ADC12ENC=1 on entering the PWM interrupt handler, and then later on in the PWM interrupt handler set ADC12ENC=0?

  • 0
    Intellectual 475 points

    Doah - and just writing the above, I find ADC12SC in ADC12CTL0 - and that seems less of a cludge.  (With ADC12SHSx-0x0 - so selecting ASC12SC is trigger input). Anyway interested to hear peoples thoughts.

  • 0 in reply to Helic Chi
    Intellectual 475 points

    Bit confused on that example. In the configuration of ADC10 it says:

      ADC10CTL1 = ADC10SHP + ADC10SHS_2 + ADC10CONSEQ_2; // sampling timer, TimerB0.0 trigger 
                                            // trigger, rpt single channel

    Now my reading of salu208q it says:

    Two different
sample-timing methods are defined by control bit ADC10SHP, extended sample mode and pulse mode.

    And that seems to be what ties the ADC sample to Timer B. Pulsed sample mode which is what seems to be selected, is described below as:

    The pulse sample mode is selected when ADC10SHP = 1. The SHI signal triggers the sampling timer.
The ADC10SHTx bits in ADC10CTL0 control the interval of the sampling timer that defines the SAMPCON
sample period, tsample. The sampling timer keeps SAMPCON high after synchronization with AD10CLK for a
programmed interval of tsample. The total sampling time is tsample plus tsync (see Figure 27-4).
The ADC10SHTx bits select the sampling time in 4x multiples of ADC10CLK.

    And that doesn't seem to say it is controlled by Timer A/B.

    Have I misunderstood?

    Ah Fig 27-1 clarifies SHP if just a way of bypassing "Sample Timer" in the ADC10 code - but doesn't alter where the timing source comes from; which is controlled by ADC10SHSx - which is set to a Timer trigger. In the MSP430F5529 document - can see where those Timer Trigger are set.

    Ah found it. In msp430f5529.pdf it says in table 9-14

    ADC12 (internal) (2)
ADC12SHSx = {2}

    For TB0 - so yes that seems to be how it synchronises. So as usual just reading enough of the document finds the solution!

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