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MSP430F2618: Reset states and initial conditions.

Part Number: MSP430F2618

Hi. I wrote a PDF. but they seem to be disallowed, so here are scans. 'Hope this works.

JC

  • A WDT "security key violation" (wrong password) generates a PUC. This isn't mentioned in Fig 2-1, but it is in the 2nd paragraph below the figure.

    The table on p. 22 ("Register Bit Conventions") shows the initial register value designations -- the form "-(0)" means "after POR", which implies it is not changed by a PUC, i.e. the device keeps running.

    Supposing you can't really make use of this behavior, the best strategy might be to reset ("de-initialize") the device as part of the initialization sequence. In some cases a strategic ordering (using "=" rather than "|=") of register writes might be enough.

  • Thank you Bruce.

    What would I do to reset ("de-initialize")  the device? Writing all the registers that matter would take a lot of code, especially given that some are not initialized to zero.

    What I wish to have is the exact states that follow a power up. If the WDT doesn't cause this, is there anything that would? i.e. force a POR without powering down.

  • I don't know of a mechanism for generating a POR from software. The F5 series has the PMMSWBOR mechanism; you might  be able to do something similar with the SVS, though that's not mentioned as a feature. (I haven't worked with an F2 device that had an SVS.)

    When I did this a long time ago, I recall that I was able to harden my initialization sequences mostly by using "=" rather than "|=" and being careful about ordering. The ADC was the only real bother, and even that just required 4x register writes to make it stop.

  • Ì shall look up the PMMSWBOR mechanism (if there is one in my processsor) )and also look into the BOR.

    The PORON bit in the SVS register looks interesting.

    It would be easy to set the threshold to a voltage higher than the supply voltage.

    -------------------------------------------

    POR on. This bit enables the SVSFG flag to cause a POR device reset.
    0b = SVSFG does not cause a POR
    1b = SVSFG causes a POR

    --------------------------------------------

    I shall also review my initializations because I suspect I use some |= lines on the assumption that those registers are in default states.

    Cheers.

  • I believe my processor has no PMMSWBOR mechanism.

    I tried resetting the processor with the instruction
    SVSCTL = 0xE0 + PORON;
    That generates a POR, but unfortunately the SVS register is not cleared by POR, and so the processor cannot restart.
    Here is what the reference document says about the SVS register:
    (1) Reset by a brownout reset only, not by a POR or PUC.

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