MSP430 interface with M25P10A flash on SPI

sunil sharma

Other Parts Discussed in Thread: MSP430FG4619

Hi all

I am trying to write data and then read the data from the flash on SPI.
The flow of the code is like this

Chip Select Low
Write Enable
Bullk/Sector Erase(write disabled after Erase)
CS Hi

CS Lo
write enable
Page program(sends address bytes and then the data bytes)- write automatically disabled
CS Hi

CS Lo
Read data (sends address bytes and then receives data bytes)
Chip Select High

However, on reading the programmed address, I am getting only FFs. Is it happening because the page program instruction is not getting executed, or am I not able to read
properly. (Write Protect and Hold are disabled)

The code is attached, have taken care to configure the MSP430 properly-MSB first,master, 3-pin,SMCLK/255 and I can see the clock, CS and Data In on Scope

Pse help....

Thanks

over 14 years ago

0 sunil sharma over 14 years ago

Intellectual 495 points

The code is attached...

Fullscreen 2134.msp.txt.txt Download

#include  "msp430xG46x.h"

RST equ  02h;  P8.1 is Chip Select, PIN 1 => address 02h in P8OUT/P8DIR


            RSEG    CSTACK                  ; Define stack segment
            RSEG    CODE                    ; Assemble to Flash memory
;-----------------------------------------------------------------------------
RESET       mov.w    #SFE(CSTACK),SP    ;#02100h,SP; Initialize stackpointer
           
main        nop
StopWDT     mov.w   #WDTPW+WDTHOLD+WDTNMI+WDTTMSEL+WDTSSEL,&WDTCTL  ; Stop WDT
setupSVS    mov.b   #018h,&SVSCTL            ;Vth = 1.9V
setupRTC    mov.b   #30h,&RTCCTL
            bis.b   #RTCBCD,&RTCCTL
;----------------------------------------------------------------
;CONFIGURE PORT8 FOR CHIP SELECT(as GPIO-active low)
;----------------------------------------------------------------
SetupP8     mov.b   #00h,&P8SEL         ;CONFIGURE AS GPIO
            mov.b   #00000010b,&P8DIR         ;CONFIGURE P8.1 as OUTPUT for CS of FLASH                    
;----------------------------------------------------------------            
;Configure port 7 for SPI
;----------------------------------------------------------------
SetupP7    bis.b   #0Eh,&P7SEL             ; P7.3,2,1 option select as USCI_A0                                         
;----------------------------------------------------------------
;SETUP MSP430 FOR RTC INTERFACE on SPI
;----------------------------------------------------------------            
SetupSPI   bis.b   #UCSWRST,&UCA0CTL1           
;Initialize all USCI registers with UCSWRST=1          
           bis.b   #UCMST+UCSYNC+UCMSB,&UCA0CTL0;3-pin, 8-bit SPI master,MSB first
           bis.b   #UCSSEL_2,&UCA0CTL1     ; SMCLK=1 MHz
           mov.b   #255,&UCA0BR0           ; SMCLK/255
           clr.b   &UCA0BR1                ;
           clr.b   &UCA0MCTL               ; No modulation
;Clear UCSWRST
           bic.b   #UCSWRST,&UCA0CTL1      ; Initialize USCI state machine                                
;----------------------------------------------------------------------------
;WRITE INCREMENTED DATA TO PAGE 001000 IN FLASH => WRITE ENABLE+BULK ERASE then Write Enable +PAGE PROGRAM , THEN READ
;----------------------------------------------------------------------------
;  WRITE ENABLE INSTRUCTION CODE                                   
           bic.b  #RST,&P8OUT      ;MAKE CS LOW BY SETTING P8.1 LOW, SELECT SLAVE - RST = 00h
           
           mov.b  #00000110b,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE              
TX	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz TX   
           
	   mov.b  #11011000b,&UCA0TXBUF   ;  SECTOR INSTRUCTION CODE1101 1000
           ;mov.b  #11000111b,&UCA0TXBUF   ;  BULK ERASE INSTRUCTION CODE

;3 byte Address for Sector Erase- 00 00 01 - Sector 1 any address inside the sector
           
           mov.b  #00h,&UCA0TXBUF   ;              
SE1	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz SE1
           
           mov.b  #00h,&UCA0TXBUF   ;               
SE11	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz SE11
           
           mov.b  #01h,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE              
SE111	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz SE111
           
           bis.b  #RST,&P8OUT      ;MAKE CS HI
           
;   WAIT for Bulk erase(nop/monitor write in progress bit of status register)
	   mov.w   #100h,R11               ; Add time between transmissions to
Delay      dec.w   R11                     ; make sure slave can keep up
           jnz	Delay 
           
;  PAGE PROGRAM INSTRUCTION CODE
           bic.b  #RST,&P8OUT      ;MAKE CS LOW
           mov.b  #00000110b,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE
           
           mov.b  #00000010b,&UCA0TXBUF   ;  PAGE PROGRAM INSTRUCTION CODE              
TR	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz TR
           
;3 byte Address for Page Address- 00 10 00 
           
           mov.b  #00h,&UCA0TXBUF   ;              
TX1	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz TX1
           
           mov.b  #10h,&UCA0TXBUF   ;               
TX11	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz TX11
           
           mov.b  #00h,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE              
TX111	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz TX111
        
; Txn of data
                      
           mov.b  #05h,NO_OF_BYTES ; down counter   NO_OF_BYTES_WRITE
           mov.b #00h,R5;          Incremented Data to be txd
Mainloop   mov.b  R5,&UCA0TXBUF                 
TX2	   bit.b #UCA0TXIFG,&IFG2	;TX Buffer ready
	   jz TX2
           
           inc.b R5;
           dec.b NO_OF_BYTES               ;Tx 256 characters
           jnz Mainloop       

STOP       bis.b   #RST,&P8OUT     ; CS high to terminate transmission 
;----------------------------------------------------------------------------
;READ FROM FLASH - PAGE 001000 SAY 1ST BYTE
;----------------------------------------------------------------------------       
           bic.b   #RST,&P8OUT     ; CS Low to start transmission

;  READ DATA BYTE INSTRUCTION CODE             
           mov.b  #03h,&UCA0TXBUF   ;  READ DATA BYTE INSTRUCTION CODE              
loop	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz loop 
           
;3 byte Address for location(000000) to be read
           mov.b  #00h,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE              
RX1	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz RX1
           
           mov.b  #10h,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE              
RX11	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz RX11
           
           mov.b  #00h,&UCA0TXBUF   ;  WRITE ENABLE INSTRUCTION CODE              
RX111	   bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	   jz RX111
           
;  START READING DATA 
           mov.b  #05h,NO_OF_BYTES ; down counter
           
Mainloop1   mov.b  #01h,&UCA0TXBUF  ;dummy byte for reception
;TX_2	    bit.b #UCA0TXIFG,&IFG2   ;TX Buffer ready
	    ;jz TX_2            
       
RX2	   bit.b #UCA0RXIFG,&IFG2	;RX Buffer ready
	   jz RX2            
           mov.b  &UCA0RXBUF,R9
           
           dec.b NO_OF_BYTES               ;Tx 256 characters
           jnz Mainloop1       

           bis.b   #RST,&P8OUT     ; CS high to terminate transmission             
;------------------------------------------------------------------------------
            COMMON  INTVEC                  ; Interrupt Vectors
;------------------------------------------------------------------------------
            ORG     RESET_VECTOR            ; MSP430 RESET Vector
            DW      RESET                   ;
            END

Thanks.........

0 sunil sharma over 14 years ago in reply to sunil sharma

Intellectual 495 points

Hi all

Have made CS high after each command but the code is still not working (Still reading FFs).

I wanted to know whether CS is to be made high at byte boundaries OR

after each instruction sequence/command. Instruction sequence as per my understanding is Instruction code/command+3 address bytes + data in /out bytes.

For eg. in the case of Page Program (to write to flash page after bulk erase)

I am following this sequence presently-

CS low

Write Enable

CS High

CS low

Page Program

3 byte address

data byte in

CS high

CS low

read data

3 byte address

Transmitting dummy bytes for reception

CS high

Also I am presently not checking the Write in progress bit of Flash Status register as I am single stepping and giving a delay after Bulk Erase and Page Program instructions. However I am monitoring the TXBUF and RXBUF of the SPI.

Is this OK???

0 sunil sharma over 14 years ago in reply to sunil sharma

Intellectual 495 points

Hi all ....

Can anyone help me out on this topic please.....

0 BrandonAzbell over 14 years ago in reply to sunil sharma

TI__Guru 64840 points

Are you observing the proper signaling behavior between the microcontroller and the flash memory device on the SPI bus using an oscilloscope?

I would suggest utilizing this type of equipment to verify the transactions being sent from the microcontroller are consistent with what is expected by the memory device. The expected transactions should be documented in the collateral (datasheet, user's guides, etc) of the memory device.

0 sunil sharma over 14 years ago in reply to BrandonAzbell

Intellectual 495 points

Hi Brandon

I am watching the signals also on scope and am getting SCLK, CS and Data In. Although, I haven't watched them together on the scope as I don't have test points. But the CS is toggling correctly.

However I am not seeing anything on Data out. As nothing is being read.

As per M25P10A datasheet Iam using MSB first and CLKPOL=0 and CLKPH=0.

I tried reading the Status register of the flash after Write Enable but the Write Enable latch is not set. (Write enable is reqd before any write/erase)

Also, regarding checking buffers, Iam checking the TX int flag and Rx int flag for the Tx Buffer and Rx Buffer.

Is this sufficient or do I have to check the UCBUSY bit as well of the UCSTAT register(using USCI_A0 port- P7 of MSP430FG4619).

So I dont think that erase is happening.

Regarding the read routine- Iam writing the instrxn code followed by the 3 byte address as per the instruction code.

Thereafter Iam transmitting some dummy bytes in oredr to receive from flash memory.

Thanks

0 Arte8bits When technology becomes art over 14 years ago in reply to sunil sharma

Prodigy 230 points

Hi sunil,

I'm 95% sure that your problem is that your CS signal is going high before the bytes are transmitted to the slave device. When you put a byte for writting in a microcontroller, you are writting this byte into a buffer and then, there is a specific hardware in charge of getting this byte and transmitting it. Therefore if you put CS high inmediatly after writting the byte, your SPI port should not work properly.

So there is not enough the verification of CS signal going up, you need to check the entire SPI port.

You can test if this is your case, try to include a 100 ms delay before put the chip signal high, and if it works, you could optimize it. For instance, there are flags that indicate that the hardware has finished the task of transmitting the byte, and you could include a security delay of only a few of microseconds after this flag signal.

Best regards.

---

www.javierlongares.com

http://www.javierlongares.com/arte-en-8-bits/

0 Jens-Michael Gross over 14 years ago in reply to Arte8bits When technology becomes art

Guru 227245 points

Arte8bits When technology becomes art said:
I'm 95% sure that your problem is that your CS signal is going high before the bytes are transmitted to the slave device.

By reading the sourc ecode, I'm 100% sure that youi're right :)

Indeed, teh code waits for TXIFG being set before CS goes high. But when TXIFG is set, thsi only means that the last byte has been moved from the buffer regsiter to the output shift register and the buffer register is empty.
It does NOT mean that the byte that has jus tleft the buffer is already sent. So CS goes high a whole byte too early.

The bit to check whether all transactions are completed is UCBUSY bit.

Arte8bits When technology becomes art said:
You can test if this is your case, try to include a 100 ms delay before put the chip signal high, and if it works, you could optimize it.

Some slaves require a certain delay anyway, before settign CS low before the transmission starts, and a certain delay for setting CS high after the transmission was completed. This should be stated in the slave datasheet.

Also, the wait delay between the write command and teh following read is only ~768 MCLK cycles. So on 1MHz less than one millisecond. I fear the slave isn't done writing after this short delay.

0 sunil sharma over 14 years ago in reply to Jens-Michael Gross

Intellectual 495 points

Hi everyone

Thanks a lot for your help .....
I did the following - checked UCBUSY =0 before every CS high, and introduced some delay as well.
This is of course mandatory for SPI to work.....

But still due to my mistake the code was not running....
Actually with M25P10A only CLKPOL=0 and CLKPHA=0 or POL/PHA=1,1 works.

I was setting UCCKPH=0 which was resulting in the problem......because this actually stands for CPHA=1.

Changing this as well as regular checking of UCBUSY helped me work this out.....

Thanks a lot for your help and support....

Regards

---Sunil

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MSP430 interface with M25P10A flash on SPI