Other Parts Discussed in Thread: MSP430F6723,
Tool/software:
Hi,
One of our devices built around MSP430FR2433 is connected to another device built around MSP430F6723. Once per second F6723 will wake up FR2433 by toggling a GPIO. After waking up, FR2433 will output some data via UART. The following is code to initialize FR2433:
WDTCTL = WDTPW | WDTCNTCL | WDTSSEL_1 | WDTIS_3; // Start watchdog timer
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode to activate previously configured port settings
// Setup clock
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_3; // Set DCO = 8MHz
CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz, default DCODIV as MCLK and SMCLK source
// Code to initialize UART
UCA1BR0 = 52; // 8000000/16/9600
UCA1BR1 = 0x00;
UCA1MCTLW = 0x4900 | UCOS16 | UCBRF_1;
UCA1CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
// Code to enter into sleep
__bis_SR_register(LPM3_bits | GIE); // Enter LPM3
// Code to wake up from GPIO interrupt
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = PORT2_VECTOR
__interrupt void Port_2(void)
#elif defined(__GNUC__)
void __attribute__((interrupt(PORT1_VECTOR))) Port_2(void)
#else
#error Compiler not supported!
#endif
{
if (P2IFG & BIT7)
{
P2IFG &= ~BIT7;
__low_power_mode_off_on_exit();
}
}
To a large degree FR2433 works as expected, but occasionally the UART output from FR2433 are gibberish, presumably because the baud rate is way too off for F6723 to recognize. If the output from FR2433 remains gibberish for 15 consecutive times, F6730 will restart itself and re-initialize F2433. This will get the whole setup to work again. Alternatively, if F6723 sends a command to restart FR2433, that will usually get back to again. This happens on average once every 3 days and to every FR2433 device. Meanwhile Similar devices built around MSP430I20XX rarely does this.
My question is, how do we improve the reliability of UART output from FR2433 for long term? It seems the clock on FR2433 will drift over time. I assume an external crystal can help, but we don't have much space on PCB. So I am wondering if there are any other options.
Thanks,
ZL
