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Trying to understand DCOCTL and BCSCTL

I can't seem to find anything that explains how to use DCOCTL and BCSCTL. I'm new to embedded programming (Although I consider myself pretty good at C and C++). I'm using the MSP430 Launchpad with the external osc soldered on.

 

My goal is 16MHz but for now I'm aiming at a value in the datasheet:

DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 15.25 MHz

 

How would I go about settings this up? It looks like I have to setup DCOCTL and BCSCTLx (Why are there three?) 

Looks like DCOCTL should be assigned like so:

 

/* DCO(15,3) is 15.25MHz */

DCOCTL |= 0xF3;

I don't really understand how to do anything with BCSCTLx as I don't understand why their are three of them, but I can assume its how I setup the internal caps and to enable the external crystal.

 

Edit: (I looked at these in the debugger (not sure why I didn't look at them before!)). Should it go something like this:

/* XT2OFF bit off, this should enable XT2? */

BCSCTL1 &= ~XT2OFF;

/* Set to 12.5 pF, all other settings look good? */

BCSCTL3 |= XCAP_3;

  • Hi,

    I assume you have some problems to find the correct documentation....

    The documentation of MSP430 is structured into chip specific information and family information.
    The chip specific information can be found in the datasheet (information like memory map, timer capture input signals, electrical parameters, ....).

    In the datasheet you also find the functional blockdiagram that shows you which peripheral modules are available on the different chips. The description for these modules can be found in an MSP430 family User's Guide (e.g. MSP430x2xx Family User's Guide). In this document you find all the peripheral modules described.

    Here is the link the actual MSP430x2xx User's Guide: http://www.ti.com/lit/ug/slau144h/slau144h.pdf

    BCSCTLx basically means that instead of the "x" a number is used. In case of the 2xx family there is BCSCTL1, BCSCTL2, and BCSCTL3. The clock module is configured with these control registers.

    Based on the module description you can find out which values has to be written in the different registers:

    DCOCTL = 0x60;     // DCOx bits = 3, MODx bits = 0

    BCSCTL1 = 0x0F;   // RSELx bits = 15

    the other registers are used to select the setting for pre-dividers and crystal oscillator settings.

    Note, when you change the frequency via these control registers think about what will happen after each code line! If you do not take care you may easily select a frequency for a short time that is far above the maximum specified value. This may then cause big troubles. So each setting is immediately active after execution of each instruction!

     

     

  • Okay so I made a function:

    void config_osc(void)
    {
        /* 15.25MHz */
        DCOCTL |= DCO0 + DCO1;
        BCSCTL1 |= XT2OFF + RSEL0 + RSEL1 + RSEL2 + RSEL3;
        BCSCTL3 &= XCAP_3;
    }


    From my understanding this IC doesn't have XT2OFF so it doesn't matter if I set it, but I can't seem to find anything about enabling an external osc through XIN/XOUT. Also I know it's not using it as I can stall the osc (bridge the two pins together) and the code continues to run (led flashing). What am I missing?

  • I suggest you take a look at Figure 5-1 of the MSP430x2xx Familiy User's Guide as it will provide some assistance in visualizing the configuration of the Basic Clock Module.  You will see there are 3 possible sources for MCLK (Main System Clock servicing the CPU) and SMCLK (SubSystem Clock which services peripherals) which include the VLOCLK, XT1 and DCO on devices without XT2.

    Section 5.2 describes that after a Power Up Clear event (PUC), the DCOCLK is the source for MCLK and SMCLK.

    Section 5.2.7.1 describes how to source MCLK from a crystal.

  • If sombody needs this, I have another starting point for 1Mhz (CALBC1_1MHZ)

    BCSCTL1= 0x87;

    DCOCTL = 0x20;

  • Samo, the required DCO config settings for getting ~1MHz are different for each and every MSP.
    This is why TI provides calibration values which are determined by try and error (well, sort of) at production time.

    There's a software found somewher ein this forum, which changes the DCO settings until the DCO output matches a known external clock source (usually a 32kHz watch crystal, but any known external frequency will do).

    Tis is basically how the FLL in 4x and 5x family works too.

  • I understand this. I actually used the above mentioned file for calibration, but if somebody doesn't have 32kHz crystal at hand, the base settings are still a good starting point.

  • Samo Fabcic said:
    if somebody doesn't have 32kHz crystal at hand, the base settings are still a good starting point

    Well, the same setting that produces 1MHz on one MSP may produce 500kHz or 2MHz on a different MSP. So the calibration settings of one MSP don't serve better as a starting point than what you can read directly form the datasheet DCO frequencies table.

    Of course, if you have multiple MSPs form the same batch, chances are high that the required DCO settings are somewhat similar. So you can copy from one chip with intact settings to another one where you lost them.
    But the settings of a chip of unknown silicon revision and production batch are not better suited than plain guessing.

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