I'm in the process of modifying the TI version of the
Bootstrap Loader (BSL) for the MSP430F5437A, and I'm confused about some of the
things in the TI version. I'm using CCS 4.2.3. The
linker command file divides the 2k of BSL memory into the following contiguous
segments:
MEMORY
{
...
ZAREA
: origin = 0x1000, length = 0x0010
BSL430_VersionM : origin = 0x1010, length =
0x0004
ZAREA_CODE :
origin = 0x1014, length = 0x002E
BSLSIG
: origin = 0x17F0, length = 0x0010
BSL_FLASH : origin
= 0x1042, length = 0x07AE
...
}
where I've left out the MEMORY specs that are irrelevant. I more or less
understand the ZAREA specification. The TI document on creating a custom
flash based BSL (slaa450a) defines it as a small region of memory that can be
read or jumped to by programs from anywhere in memory even when the BSL is
protected by the SYSBSLPE bit in the SYSBSLC register, which otherwise renders
the BSL memory inaccessible. I say "more or less" because the
only documentation of this feature seems to be in slaa450a, and not for
instance in the 5x Family Users Guide (slaa 208i). So my first question
is, have I missed something here? Is the ZAREA behavior documented in
more detail in the normal documentation, or is it only documented in the Flash
BSL documentation?
The question seems particularly relevant because of the other odd memory
segments that are defined here. I can imagine the version info being
forced into a specific address so you can tell what BSL you have from an
examination of the image, without having to run the code. But I'm unclear
why the flash memory used for code has been divided into "ZAREA_CODE"
and "BSL_FLASH". These two regions are contiguous, and there is
no documentation that I've been able to find or anything I can figure out about
why these regions should behave differently. So why are they treated
differently? Designating a section as "zarea code" seems to
imply that it may have special access permissions, but I can't find anything
about it. Does anyone know what is going on here, or where I can find it
documented? Can these two regions be
combined into one so that the linker can decide how to best use the memory?
Steve