Question about MSP430 Timer_A

Thank you for your help.

I wonder if you could help with another question:

I'm gonna use SPI module in MSP430F5418A to accomplish full duplex SPI communication with CPLD. Do I have to write the TX function and RX function together?

And there is a register named modulation control in SPI module. What does it mean? And how to use it? Do I have to set the value of this register when I use SPI

module?

Thanks

Nick

Nick Carter said:

Do I have to write the TX function and RX function together?

TX and RX share the same interrupt, so at least the interrupt handler must be combined.
How you do the actual transfer is up to you. You can do it inside the ISR, you can do it witout an ISR at all.

SPI is synchronous bi-directional. You'll need to write something to get something. If you don't write something, no clock is generated and nothing is received as well.

Nick Carter said:

there is a register named modulation control in SPI module.

It is in teh USCi module, but in SPI mode, it is meaningless and should be written 0 (or left untouched). It only has a meaning in UART mode, where it controls bit timing modulation for asynchronous transfer. Since on SPI, the clock is sent by the master (and therefore does not need to be on an exact frequency), no modulation is necessary. (in fact, the clock on SPI can differ significantly for each single bit and it won't hurt the transfer).

 

Thank you for your answer. I have one more question:

You said TX and RX share the same interrupt, so did the user guide. But the table of interrupt vector shows that there are two different interrupt vectors for Tx and Rx.

I'm confused. Please help!

Thank you

Nick

Nick Carter said:

the table of interrupt vector shows that there are two different interrupt vectors for Tx and Rx.

Where? The vector table in my  copy of the 5418A users guide reads 'USCI_A0 Receive/Transmit", "USCI_B0 Receive/Transmit" and so on. One vector, two function: Receive+Transmit.
There are, however, individual interrupt flags UCRXIFG, UCTXIFG etc.listed. And there are more (UCNACKIFG for USCI_Bx I2C mode etc.) One interrupt vector, one ISR, but multiple causes for this ISR being called (this is what "(1) Multiple source flags" means.

Could you give a link which is linked to the 5418A user's guide you have?

Cause my document found on TI website is different from yours in the USCI section.

The document's link which I found on TI website:http://www.ti.com.cn/cn/lit/ug/slau208i/slau208i.pdf

You can see that there are two interrupt vectors in UART interrupt vertor register.

Thank you

Nick

Nick Carter said:

Could you give a link which is linked to the 5418A user's guide you have?

Sorry, typo. I meant the datasheet, not the users guide ;) The users guide is for all 5x/6x deices, the datasheet is 54xxA specific.

Nick Carter said:

You can see that there are two interrupt vectors in UART interrupt vertor register.

Ah, well, that's the cause of confusion. The interrupt vector register is something different. It has nothing to do with the global interrupt vectors and the global interrupt vector table.

The IV register is a convenience register that gives, when read, an 'interrupt source' value of the highest priority pending interrupt of this module, at the same time clearing the associated IFG bit.

So if oyu enter the RXTX ISR and read the USCIxyIV register, yo'll get a value of 0, 2 or 4, where 0 means 'no interrupt pending' (if it has been cleared by hardware or software while the processor was still entering the ISR - it can happen on I2C but also if the main code was clearing the IFG bit the very moment the interrupt was triggered)

'2' stands for 'there's something in the RX buffer' and '4' means 'the TX buffer needs something to be stuffed in (or maybe I twisted 2 and 4). In I2C mode, there are more.

The reason why it is called a vector register is because the most efficient way to use it is to add its value to the current program counter in assembly. Afte rthe add isntruction, there is a matrix of jump commands. Depending on the content of the IV register, the PC gets incremented by 0, 2,4... which means it wille jump to and execute the first, second... jump command. Much faster than testing for IFG bits.

For C, the compiler offers a similar funcitonality with the 'even_in_range()' intrinsic.

switch (__even_in_range (UCA0IV, 4))

will produce a highly efficient code that takes only 6 MCLK cycles to jump to the proper case, as it tells the compiler that UCA0IV will result in an even number in the range of 0..4.