MSP430F2618: DAC12 Fullscale range selection issue. (Power consumption of DAC12 module may be increased due to DAC12IR bit selection)

Part Number: MSP430F2618

Tool/software:

Hi

I'm using MSP430F2618 DAC12 modulel to generate an analog value as the Vin+ input of a comparator. the schematic is shown as following. The reference voltage is supplied by a MAX9015 which has 1uA output capacity.

First I set DAC12IR bit as 0, then the functionality of the circuit works good.

Then I want to increase the output resolution of DAC12 so I set DAC12IR bit as 1.

After that, I found the DAC12_1 port doesn't output properly and the Veref+ was pulled down. The datasheet and userguide dosen't say any thing about if the power consumption of DAC12 module will be increased due to DAC12IR. But the fact is that it seems so.

So my question why this issue occurs when  DAC12IR bit is set?And is there any way to solve this issue without change hardware design?

Thank you!

  • You can try to set the DAC12AMPx with 111 as below

    That to enable the internal buffers for your input and out put .

  • Thank you for your reply, but DAC12AMPx has already been set as 111. that not work -_-! 

    DAC12AMP0  DAC12AMP1  DAC12AMP2  DAC12SREF1 DAC12OPS bits are set as 1;

    DAC12GRP  DAC12ENC  DAC12IE  DAC12DF DAC12LSEL0  DAC12LSEL1   DAC12RES  DAC12SREF0  are set as 0;

    DAC12CALON is set during DAC1 init and then automatically cleared by hardware;

    DAC12IFG is not used, I guess it remains as 0.

  • Data Sheet (SLAS541L) Sec 5.53 says the Veref input impedance with IR=0 is 20MOhms, but with IR=1 is about 48kOhms. My calculator says that (at 1.236V) this is the difference between  0.061uA and 26uA drawn through Veref.

    Note (5), as well as Sec 5.49 Note (2), suggest that the Veref /3 for IR=0 1 is done via a resistor divider, which evidently adds quite a lot of reduces the impedance.

    I don't see any obvious way to avoid this. 

    [Edit: Got the commentary backwards. I'm pretty sure the numbers are right, though.]

  • Thank you Bruce, I think that is the final conclusion! Hardware design must be changed if I have to use higher DAC output resolution.

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