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MSP430F1611: Crystal Fire Up - BCSCTL1.XT2=1

Part Number: MSP430F1611

Tool/software:

Hi team,

This is a follow up to the related question where the customer is placing the MSP430 on the board without it being programmed. We've also found out that once the crystal begins to oscillate and runs the program, it will continue start up on subsequent power-cycles. We also know that the program sets BCSCTL1.XT2=1.

  1. What is the difference between BCSCTL1.XT2=0 and BCSCTL1.XT2=1 as far as the crystal being able to fire up?
  2. Is it possible to use a debugger to set BCSCTL1.XT2=1 after the part is programmed and before the crystal runs the first time?

The protocol now is:

  1. Program via JTAG
  2. Cycle power

Could it be changed to:

  1. Program via JTAG
  2. Use a debugger to set BCSCTL1.XT2=1
  3. Cycle power to let the program run

Does this sound like a feasible solution?

Thanks,

Luke

  • Following up with some more info we just receieved:

    They had a chance to look at the code and as it turns out, are using LFXT1 not XT2. Here is the startup code.

     

    ; Description:
    
    ;   The startup code is executed following a CPU Reset and performs the
    
    ;               following tasks:
    
    ;                               1)            Disable all interrupts.
    
    ;                               2)            Toggle the watchdog timer.
    
    ;                               3)            Configure the master clock (MCLK) to use the 7.2 MHz LFXT1 clock.
    
    ;                                               The sequence to switch the MCLK source from the
    
    ;                                               digitally-controlled oscillator (DCO) clock to the LFXT1 clock is:
    
    ;                                                               a) Switch on the crystal oscillator
    
    ;                                                               b) Clear the OFIFG (oscillator fault interrupt) flag
    
    ;                                                               c) Wait at least 50 µs.
    
    ;                                                               d) Test OFIFG, and repeat steps 1 – 4 until OFIFG remains cleared.
    
    ;                               4)            The MCLK and ACLK are configured to use the 7.2 MHz LFXT1 clock.
    
    ;                                               The SMCLK is configured to use the DCO (RSELx = 4, DC0x = 3
    
    ;                                               MODx = 0, DCOR= 0).
    
    ;                               5)            Initialize stack pointer to 0x38F8.
    
    ;                               6)            Call InitWatchdog() to configure the watchdog timer.
    
    ;                               7)            Clear the Boot Monitor’s blank static storage (.bss) section in RAM.
    
    ;                               8)            Copy the Boot Monitor’s initialized data (.data) from Program Flash to RAM.
    
    ;                               9)            Toggle the watchdog timer.
    
    ;                               10) Jump to main() of the Boot Monitor. If ever return, jump to the
    
    ;                                               reset vector (i.e. step #1).
    
    ;
    
    ;============================================================================
    
     
    
    ; ________________ Macros ___________________________________________________
    
    ; ________________ Constants ________________________________________________
    
    _g_nStackStart      equ $38f8
    
     
    
    ; ________________ Code _____________________________________________________
    
     
    
                    PUBLIC  Reset
    
                    PUBLIC  _g_nStackStart
    
     
    
    #include "msp430x16x.h"
    
    ; Create sections
    
            .data
    
            .bss
    
     
    
    ; Go to code section.
    
    ;        .code
    
      ASECT "STARTUP"
    
     
    
     
    
    ; Executed upon reset
    
    Reset:
    
     
    
    ; Disable all interrupts
    
            dint
    
     
    
    ; Toggle the watchdog timer
    
    ;        mov     #WDTPW+WDTCNTCL,&WDTCTL
    
     
    
    ; Select LFXT1 (HF mode) for MCLK
    
            bic     #OSCOFF,SR                  ; Turn on osc.
    
            mov.b   #XTS+RSEL2+XT2OFF,&BCSCTL1  ; HF mode, resistor select of 4, XT2 Off
    
    _loop1: bic.b   #OFIFG,&IFG1                ; Clear OFIFG
    
            mov     #0FFh,R15                   ; Delay
    
    _loop2: dec     R15
    
            jnz     _loop2
    
            bit.b   #OFIFG,&IFG1                ; (re)test OFIFG
    
            jnz     _loop1                      ; Repeat test if needed
    
            mov.b   #SELM1+SELM0,&BCSCTL2       ; Select LFXT1CLK
    
     
    
    ; Setup the SMCLK to run off of the DCO
    
            mov.b   #DCO0+DCO1, &DCOCTL         ; DCO frequency select of 3
    
     
    
    ; Set up stack.
    
            mov.w   #_g_nStackStart, sp
    
     
    
    ; Initialize Watchdog
    
    ;        call #_InitWatchdog
    
            mov     #WDTPW+WDTHOLD,&WDTCTL      ; disable the watchdog
    
     
    
    ; Zero the bss.
    
            mov.w   #SFB(UDATA0), r15                                                              ; r15 = start address
    
            mov.w   #0, r14                                                                                                        ; r14 = value to set
    
            mov.w   #SFE(UDATA0)-SFB(UDATA0), r13 ; r13 = number of bytes to set
    
            call    #_memset
    
     
    
    ; Copy from initialised data section to data section.
    
            mov.w   #SFB(IDATA0), r15                                                                ; r15 = destination
    
            mov.w   #data_init_begin, r14                                                          ; r14 = source
    
            mov.w   #data_init_end-data_init_begin, r13            ; r13 = number of bytes to copy
    
            call    #_memcpy
    
     
    
    ; Toggle the watchdog timer
    
    ;        mov     #WDTPW+WDTCNTCL,&WDTCTL
    
     
    
    ; Call user entry point void main(void).
    
            call    #_main
    
     
    
    ; If main() returns, kick off again.
    
            jmp     Reset
    
     
    
    ; Heap data structures; removed by the linker if the heap isn't used.
    
            .break  
    
            .data
    
            align   WORD
    
    ___heap_start__::
    
            DW      0
    
            DW      heap_size
    
            DS      heap_size-4
    
    ___heap_end__::
    
     
    
    ; Initialise the IDATA0 section by duplicating the contents into the
    
    ; CONST section and copying them on startup.
    
            .const
    
    data_init_begin:
    
            .init  "IDATA0"
    
    data_init_end:
    
     
    
      END

  • Hi,

    If customer used a debugger via JTAG to set the crystal configuration per the code above, would that help the crystal start on the first power up?

    Thanks,

    Luke

  • Hi team,

    Any update here?

    -Luke

  • Hi Luke,

    1.XT2 is used to set different LF crystal frequency, datasheet gives the description of this:

    Also with the user guide:

    2.This doesn't work.

    Does this sound like a feasible solution?

    Due to when user re-power the board, the debugger setting will be lost, and what setting in the program will take effect again.

    B.R.

    Sal

  • Hi Luke,

    If customer used a debugger via JTAG to set the crystal configuration per the code above, would that help the crystal start on the firs

    The JTAG setting will keep once and work after the device power up fisrtly, but after the device reset or re-power, then the debugger setting by JATG will be lost.

    B.R.

    Sal

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