MSP430F6775A: Msp430f6775a

Peter Peter

Part Number: MSP430F6775A

Tool/software:

Hi,

I would like to ask about the external crystal or XT1 mode. When is the XT1 set as default for FLL reference than on the startup does it work when the XT1 is set off ? Or is there the REFO ? Cuz I have noticed the default configuration and the OFC Flag is set by default and when clered and still the XT1 OFF is set to one the flag won't set back to fault. So I am confused even when default configuration uses XT1 but it is set to 1 in the startup than default configuration is not using the XT1 but REFO or ? Also the xcap defines capacitance that I have connected externally on xin and xout ? Cuz I have noticed that it has no effect on whether set or not while XT1off bit is 0 so the external crystal is on .

1 month ago

0 Brian Dempsey 1 month ago

TI__Intellectual 2495 points

Hi Peter, apologies I am trying to follow the question here, are you asking if XT1 is used in the default configuration? Can you please clarify what you are asking?

-Brian

0 Peter Peter 1 month ago in reply to Brian Dempsey

Prodigy 170 points

Hi, I am asking whether the default configuration really matters. I mean the XT1 should be used as default for ACLK I think but if it is set as default will it really work when XT1OFF is set by default to 1 which means that it is off?

+1 Brian Dempsey 1 month ago in reply to Peter Peter

TI__Intellectual 2495 points

Hi Peter, ok I understand now. Any clock request from a peripheral module causes the clock off signal to be overridden, but does not change the setting of clock off control bit. So regardless of the XT1OFF bit status, if a peripheral is using it to source ACLK, MCLK, or SMCLK, the XT1 should still be on. You can find more information on this in the reference manual (Section 5).

-Brian

0 Peter Peter 26 days ago in reply to Brian Dempsey

Prodigy 170 points

Thank you for you answer. And is there any option how to verify that the clock is really a source for ACLK even when the bit is still off ? Or it is just that the interrupt flag is off in the register for that clock source ?

0 Brian Dempsey 18 days ago in reply to Peter Peter

TI__Intellectual 2495 points

Hey Peter, I think based on the mode of operation along with the scenarios listed in the reference manual. You could also try reading from the UCSCTL4 register during operation to check the source for the CLKs.

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MSP430F6775A: Msp430f6775a