MSP430F6775A: DCO

Hi,

Does DCOFFG will be set at free run mode or only observe this issue at debug mode?

If the external crystal is missing, you do not change the setting in the REFCLOCK. Please refer to chapter UCS Module Fail-Safe Operation in UG for more details. 

Best regards,

Cash Hao

Hi,

I have debugged the UCS setting and then set it to free running mode, stopping at the breakpoint in the last function. After resetting the flags in the initialization function, there was nothing. This part was debugged step by step, but eventually, at the final breakpoint, after communication was over and free running mode stopped, the flag was set again. However, only the DCOFFG flag was set, as I mentioned.

Hi,

This is wired. Could you share your test code here? We can take a look into it first. 

Best regards,

Cash Hao

Hi,

It is too big I am affraid but I can share UCS configuration. I am using UART in the project as well.

Hi,

UCS configuration should be fine. And the code how you check the DCOFFG flag in the application.

Best regards,

Cash Hao

void initClk()
{

UCSCTL3 |= SELREF__REFOCLK;
UCSCTL4 = SELA__REFOCLK | SELM__DCOCLK | SELS__DCOCLK;

__bis_SR_register(SCG0);

UCSCTL0 = 0x0000;
UCSCTL1 = DCORSEL_4;
UCSCTL2 = FLLD_0 | 243;

__bic_SR_register(SCG0);

// Settling time for the DCO
// 32 x 32 x 8000000Hz / 32,768 Hz = 250 000 = MCLK cycles
__delay_cycles(250000);

UCSCTL6 &= ~(XT1OFF);
UCSCTL6 |= XCAP_0;

// Timeout to reset flags
int timeToReset = 30;

// Clear fault flags
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags

// Clear SFR OF fault flag
SFRIFG1 &= ~OFIFG;

} while ((SFRIFG1 & OFIFG) && --timeToReset);

// Reduce strength
UCSCTL6 &= ~(XT1DRIVE_3);

}

I got also the eusci with pin configuration.

void initeUASCI()
{

P3SEL0 |= BIT0 | BIT1;
P3DIR |= BIT0 | BIT1;

UCA0CTLW0 = UCSWRST;

UCA0CTLW0 |= UCSSEL__SMCLK;

UCA0CTLW0 |= UCPEN | UCPAR;

UCA0BRW = 52;
UCA0MCTLW = 0x4900 | UCBRF_1 | UCOS16;

UCA0CTLW0 &= ~UCSWRST;

}

I check the DCO fault flag in the registers view. I will start the program than I will do my stuff with commnuication and than at the brakepoint I will check the registers again.

The FLL refclock should be   UCSCTL3 |= SELREF__XT1CLK;  and the SELA__XT1CLK  is also sometimes I did some tests with crystal insted of refclock thats why the xdrive and xcap is still in the configuration.

Hi,

The clock configuration looks good from my side. 

For checking the DCO fault flag. Try use the code to check the DCOFFG like below. And you can toggle an IO pin in the if loop. Let the MCU free run instead of in debug mode. Check if it will hit this if condition at free run.

if( DCOFFG  == (UCSCTL7 &DCOFFG )) {};

Best regards,

Cash Hao

Thank you for your answer I did it and unfortunately the bulb is flashing brightly. So the condition was probably met in the free run mode. What should I consider now?

Hi

Emm, one last thing to check. Have you tested only on one chip. Or you have several other boards, and they behave the same issue here? If so, I can try the code on my side and check if I can observe the same issue. 

Best regards,

Cash Hao

Hi,

I have tried also another bord with 777a model it was this code.

if( DCOFFG == (UCSCTL7 &DCOFFG )) {

P11DIR |= BIT1; 
P11SEL0 |= BIT1; 

}

And the issue persist. 

Get it. I will try to find some board to test with the code here next week.

Best regards,

Cash Hao

Okay, thank you.