Tool/software:
Hello.
I am using CCS V12.6.0.00008 & msp430fr4131. I have a weird FRAM usage in this code:
// Built with Code Composer Studio v12 //****************************************************************************** #include <msp430fr4131.h> #define us 16 // define the the value of uSec to be used in delay & _delay_cycles functions #define ms 16000 // define the the value of mSec to be used in delay & _delay_cycles functions #define _5ms 80000 // define the the value of 5mSec to be used in delay & _delay_cycles functions #define _10ms 160000 // define the the value of 10mSec to be used in delay & _delay_cycles functions #define _50ms 800000 // define the the value of 50mSec to be used in delay & _delay_cycles functions #define _100ms 1600000 // define the the value of 100mSec to be used in delay & _delay_cycles functions #define _sec 16000000 // define the the value of Sec to be used in delay & _delay_cycles functions //****************************************************************************** void initGPIO() { // make all inputs P1DIR = 0x00; P2DIR = 0x00; P3DIR = 0x00; P4DIR = 0x00; P5DIR = 0x00; P6DIR = 0x00; P7DIR = 0x00; P8DIR = 0x00; // Enable Pull up/down R P1REN = 0xFF; P2REN = 0xFF; P3REN = 0xFF; P4REN = 0xFF; P5REN = 0xFF; P6REN = 0xFF; P7REN = 0xFF; P8REN = 0xFF; // Make all inputs pulled up P1OUT = 0xFF; P2OUT = 0xFF; P3OUT = 0xFF; P4OUT = 0xFF; P5OUT = 0xFF; P6OUT = 0xFF; P7OUT = 0xFF; P8OUT = 0xFF; // Disable the GPIO power-on default high-impedance mode // to activate previously configured port settings PM5CTL0 &= ~LOCKLPM5; } //****************************************************************************** void initClock() { // Configure one FRAM wait state as required by the device data sheet for MCLK // operation beyond 8MHz _before_ configuring the clock system. FRCTL0 = FRCTLPW | NWAITS_1; __bis_SR_register(SCG0); // disable FLL CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source CSCTL0 = 0; // clear DCO and MOD registers CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first CSCTL1 |= DCORSEL_5; // Set DCO = 16MHz CSCTL2 = FLLD_0 + 487; // set to fDCOCLKDIV = (FLLN + 1)*(fFLLREFCLK/n) // = (487 + 1)*(32.768 kHz/1) // = ~16 MHz (= 15990784 Hz) __delay_cycles(3); __bic_SR_register(SCG0); // enable FLL while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // FLL locked CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; } //******************************************************** // main program variables //******************************************************** char batt_body1 = 0; // will represent the outer body char batt_body2 = 0; // will represent the outer body char batt_body3 = 0; // will represent the outer body char batt_body4 = 0; // will represent the outer body char batt_top1 = 0; // will represent the top part char batt_top2 = 0; // will represent the top part char batt_top3 = 0; // will represent the top part char batt_top4 = 0; // will represent the top part void main( void ) { WDTCTL = WDTPW | WDTHOLD; // Stop watch dog timer initGPIO(); // setup digital IO pins initClock(); // setup Clock = 16MHz _delay_cycles(_sec); // delay 1 batt_body1 = 1; batt_body2 = 1; batt_body3 = 1; batt_body4 = 1; batt_top1 = 1; batt_top2 = 1; batt_top3 = 1; batt_top4 = 1; while (1) { _delay_cycles(_sec); // delay 2 }//END OF while (1) }// END OF MAIN
That code as is, will give an FRAM usage of 798 out of 3968 20%.
If "delay 1" line is removed, it will give an FRAM usage of 776 out of 3968 19%.
But if "delay 2" line is remove (keeping "delay 1"), it will give an FRAM usage of 242 out of 3968 6%.
What also make it even more, if I keep both delays and remove all the eight batt_XXX variables assigning, it will give an FRAM usage of 264 out of 3968 6%.
So what is happening.
Thanks