MSP430FR2475: Baudrate unstable at low temperatures

Henrik Molgaard

Prodigy 20 points

Part Number: MSP430FR2475

Tool/software:

I have a product, where serial communication fails at low temperatures ( <5 degree celcius ).

I am using the DCO (16MHz) to generate my 115200 Buadrate

I am using an external XTAL at 32768hz.

This is my initialization routine:

const uint16_t u16Ratio = 488U;

/* setup pins for XCLK */
P2SEL0 |= XOUT | XIN;

/* use XCLK as ACLK */
CSCTL6 &= ( uint16_t ) ~ ( ( uint16_t ) DIVA );
CSCTL4 &= ( uint16_t ) ~ ( ( uint16_t ) SELA );

/* set FRAM wait states to 1 */
/*lint -save -e960 */
FRCTL0 = FRCTLPW | NWAITS_1;
/*lint -restore */

/* set ACLK to X Inputs */
CSCTL3 &= ( uint16_t ) ~ ( ( uint16_t ) SELREF_3 );
CSCTL3 |= ( uint16_t ) REFOLP_1;

__bis_SR_register( SCG0 ); /* disable FLL */
/* Set DCO FLL reference = REFO */
CSCTL0 = 0U; /* clear DCO and MOD registers */

CSCTL1 &= ( uint16_t ) ~ ( ( uint16_t ) DCORSEL_7 ); /* Clear DCO frequency select bits first */
CSCTL1 |= ( uint16_t ) DCORSEL_5; /* Set DCO frequency range. DCO Range = 16MHz */
CSCTL2 = ( u16Ratio - 1U ); /* f(DCOCLKDIV) = 16MHz */
CSCTL0 = __data20_read_short( TLV_16MHz_ADDR ); /* load DCO TLV trim vale to DCO Tap */

__delay_cycles( 3U );
__bic_SR_register( SCG0 ); /* enable FLL */

CSCTL4 |= ( uint16_t ) SELMS__REFOCLK; /* set REFO(~32768Hz) as MCLK -- This delay may cause fake lock when DCOTAP=0 */
__delay_cycles( 10U ); /* delay 10 FLL reference clock cycles */

while( ( CSCTL7 & ( ( uint16_t ) FLLUNLOCK0 | ( uint16_t ) FLLUNLOCK1 ) ) > 0U )
{
/* Check if FLL locked */
}
/* set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz */
/* default DCOCLKDIV as MCLK and SMCLK source */
CSCTL4 &= ( uint16_t ) ~ ( ( uint16_t ) SELMS | ( uint16_t ) SELA );

9 months ago

0 Dennis Lehman 9 months ago

TI__Guru 71086 points

Hi Henrik,

My apologies for the late response. Do you have a way to measure the TXD output bit period both at room temp and at low temperatures?

0 Henrik Molgaard 9 months ago in reply to Dennis Lehman

Prodigy 20 points

Hi Dennis.

I tried to cool the board, but did not see any change on the data line. But I have not seen the problem here. Board works as expected at any temperature.

I do not yet have any boards of the new production lot, so it may be related to something else.

But can you confirm my initialization seems correct, and can you confirm that the 2475 should compensate automatically keep the FLL with the external xtal.

0 Dennis Lehman 9 months ago in reply to Henrik Molgaard

TI__Guru 71086 points

Hi Henrik,

You indicated you are using an external 32KHz xtal for the DCO reference, but your code appears to be using the internal REFO, which is also 32KHz, but not as stable as an external xtal across temperatures.

Here is a copy of MSP430FR2475 clock initialization code that can be found in the TI Resource Explorer. This should provide stable DCO across temperatures.

    P2SEL0 |= BIT0 | BIT1;                  // P2.0~P2.1: crystal pins
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);           // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

    __bis_SR_register(SCG0);                     // disable FLL
    CSCTL3 |= SELREF__XT1CLK;                    // Set XT1 as FLL reference source
    CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_5;// DCOFTRIM=5, DCO Range = 16MHz
    CSCTL2 = FLLD_0 + 487;                       // DCOCLKDIV = 16MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                     // enable FLL
    Software_Trim();                             // Software Trim to get the best DCOFTRIM value

    CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;   // set XT1 (~32768Hz) as ACLK source, ACLK = 32768Hz
                                                 // default DCOCLKDIV as MCLK and SMCLK source

    P1DIR |= BIT0 | BIT7;                   // set SMCLK ACLK and LED pin as output
    P1SEL1 |= BIT7;                         // set SMCLK P1.7 pin as second function
    P2DIR |= BIT2;
    P2SEL1 |= BIT2;                         // set ACLK P2.2 pin as second function

    PM5CTL0 &= ~LOCKLPM5;                        // Disable the GPIO power-on default high-impedance mode
                                                 // to activate previously configured port settings

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MSP430FR2475: Baudrate unstable at low temperatures