MSP430FR2433: UART ACLK using 32KHz crystal

If you look at the guide (slau445) in the section on typical baud rates (22.3.13) you will find settings for various bits rates using 32KHz.

Hi! Thanks for your quick reply!

I looked at it and changed the settings, but did not work...

My doubt is what setting is needed to change the clock source for ACLK, in the UCA0CTLW0 register.

My current uart_init function is as follows:

// Configure pins to UART mode
    P1SEL0 |= BIT4 | BIT5;                    // set 2-UART pin as second function

    // Configure UART
    UCA0CTLW0 |= UCSWRST;                     // Put eUSCI in reset
    UCA0CTLW0 |= UCSSEL__SMCLK;

    // Baud Rate calculation (infos in UG table 22-5)
    // Settings for baud rate of 1200 using 32768 Khz clock
    UCA0BRW = 1;
    UCA0MCTLW = 0x2500 | UCOS16 | UCBRF_11;

    UCA0CTLW0 &= ~UCSWRST;                    // Initialize eUSCI

My clock setup is showed below:

P2SEL0 |= BIT0 + BIT1;                  // P2.0: XOUT; P2.1: XI1

CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;  // MCLK=SMCLK=DCO; ACLK=XT1
do
{
    CSCTL7 &= ~(XT1OFFG | DCOFFG);      // Clear XT1 and DCO fault flag
    SFRIFG1 &= ~OFIFG;
}while (SFRIFG1 & OFIFG);               // Test oscillator fault flag

The clock source is ACLK and the ACLK is using an external crystal oscillator connected in pins P2.0 and P2.1

My idea is to periodically transmit a string via UART when the watchdog timer triggers an interrupt. The code might be in LPM3 mode.

I used this dev zone snippet as a base and want to incorporate the UART function.

You say you want to use ACLK but your code says SMCLK:

    UCA0CTLW0 |= UCSSEL__SMCLK;

Yes. I did not identified the correct bit to set ACLK.

In the device's user guide, in the section of UART registers, the bits 7 and 6 are responsible for select the clock source.

The 00b should indicate the use of ACLK (considering that UCLK is a mispelling), but the communication did not work.

I also searched on CCS msp430fr2433 header file and found these bits:

UCSSEL_0 should be the setting. If it is in fact, then I am forgeting something else.

UCLK is not a misspelling. In other contexts it refers to an external clock source. But the device data sheet doesn't show an external source for UART mode. Confirming the header file.

So you can use the MODCLK or SMCLK. Keeping in mind that in low power modes SMCLK will be active when the UART requests it. Assuming you haven't disabled that feature.

So, can I use SMCLK even in the CPU in LPM3?

Regarding the SMCLK activation via USCI, I didn't know this feature exists.

Well, I'm using SMCLK at 1 MHZ in UART, but I can access LPM3 and even use WDT interrupt directives for ACLK clock sources. So, I guess that's it!