MSP430F5529 Clock Configuration for 25Mhz

Vinoth S

Other Parts Discussed in Thread: MSP430F5529

We can able to configure the clock of Msp430f5529 for 16MHZ. We required to run the clock at the maximum speed supported by the controller 25MHZ but we unable to do that.We are using Code Composer Studio v4.2.3

For 12Mhz we used below code – we can able to get Lock

WDTCTL = WDTPW+WDTHOLD; // Stop WDT

UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO

UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation

UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz

// (N + 1) * FLLRef = Fdco

// (374 + 1) * 32768 = 12MHz

// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been

// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

// UG for optimization.

// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle

__delay_cycles(375000);//

// Loop until XT1,XT2 & DCO fault flag is cleared

{

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags

SFRIFG1 &= ~OFIFG; // Clear fault flags

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

We tried for 24 Mhz with the below code – we unable to get lock

//******************************************************************************

// MSP430F552x Demo - Software Toggle P1.1 with 25MHz DCO

// Description: Toggle P1.1 by xor'ing P1.1 inside of a software loop.

// ACLK is rought out on pin P1.0, SMCLK is brought out on P2.2, and MCLK

// is brought out on pin P7.7.

// ACLK = REFO = 32kHz, MCLK = SMCLK = 25MHz

// MSP430F5529

// -----------------

// /|\| |

// | | P1.0|-->ACLK

// --|RST P7.7|-->MCLK

// | P2.2|-->SMCLK

// | |

// | P1.1|-->Port Pin toggle

// Bhargavi Nisarga

// Texas Instruments Inc.

// April 2009

// Built with CCSv4 and IAR Embedded Workbench Version: 4.21

//******************************************************************************

#include <msp430f5529.h>

void SetVcoreUp (unsigned int level);

void main(void)

{

volatile unsigned int i;

WDTCTL = WDTPW+WDTHOLD; // Stop WDT

UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO

UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation

UCSCTL2 = FLLD_1 + 749; // Set DCO Multiplier for 24MHz

// (N + 1) * FLLRef = Fdco

// (749 + 1) * 32768 = 24MHz

// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been

// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

// UG for optimization.

// 32 x 32 x 24 MHz / 32,768 Hz = 750000 = MCLK cycles for DCO to settle

__delay_cycles(750000);

// Loop until XT1,XT2 & DCO fault flag is cleared

{

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags

SFRIFG1 &= ~OFIFG; // Clear fault flags

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

/* Enable interrupts */

__bis_SR_register(GIE);

while(1)

{

// P1OUT ^= BIT1; // Toggle P1.0

__delay_cycles((unsigned int)600000); // Delay

}

We tried for 25 Mhz with the below TI sample code – we unable to get lock

//******************************************************************************

// MSP430F552x Demo - Software Toggle P1.1 with 25MHz DCO

// Description: Toggle P1.1 by xor'ing P1.1 inside of a software loop.

// ACLK is rought out on pin P1.0, SMCLK is brought out on P2.2, and MCLK

// is brought out on pin P7.7.

// ACLK = REFO = 32kHz, MCLK = SMCLK = 25MHz

// MSP430F5529

// -----------------

// /|\| |

// | | P1.0|-->ACLK

// --|RST P7.7|-->MCLK

// | P2.2|-->SMCLK

// | |

// | P1.1|-->Port Pin toggle

// Bhargavi Nisarga

// Texas Instruments Inc.

// April 2009

// Built with CCSv4 and IAR Embedded Workbench Version: 4.21

//******************************************************************************

#include <msp430f5529.h>

void SetVcoreUp (unsigned int level);

void main(void)

{

volatile unsigned int i;

WDTCTL = WDTPW+WDTHOLD; // Stop WDT

P1DIR |= BIT1; // P1.1 output

P1DIR |= BIT0; // ACLK set out to pins

P1SEL |= BIT0;

P2DIR |= BIT2; // SMCLK set out to pins

P2SEL |= BIT2;

P7DIR |= BIT7; // MCLK set out to pins

P7SEL |= BIT7;

// Increase Vcore setting to level3 to support fsystem=25MHz

// NOTE: Change core voltage one level at a time..

SetVcoreUp (0x01);

SetVcoreUp (0x02);

SetVcoreUp (0x03);

UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO

UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation

UCSCTL2 = FLLD_1 + 762; // Set DCO Multiplier for 25MHz

// (N + 1) * FLLRef = Fdco

// (762 + 1) * 32768 = 25MHz

// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been

// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

// UG for optimization.

// 32 x 32 x 25 MHz / 32,768 Hz ~ 780k MCLK cycles for DCO to settle

__delay_cycles(782000);

// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize

{

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags

SFRIFG1 &= ~OFIFG; // Clear fault flags

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

while(1)

{

P1OUT ^= BIT1; // Toggle P1.0

__delay_cycles(600000); // Delay

}

void SetVcoreUp (unsigned int level)

{

// Open PMM registers for write

PMMCTL0_H = PMMPW_H;

// Set SVS/SVM high side new level

SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;

// Set SVM low side to new level

SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;

// Wait till SVM is settled

while ((PMMIFG & SVSMLDLYIFG) == 0);

// Clear already set flags

PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);

// Set VCore to new level

PMMCTL0_L = PMMCOREV0 * level;

// Wait till new level reached

if ((PMMIFG & SVMLIFG))

while ((PMMIFG & SVMLVLRIFG) == 0);

// Set SVS/SVM low side to new level

SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;

// Lock PMM registers for write access

PMMCTL0_H = 0x00;

}

We need to run the clock at 25Mhz , the maximum speed supported by msp430f5529.

Where we went wrong

Thanks in advance

Regards,

Vinoth.S,

over 13 years ago

0 Bernhard Weller over 13 years ago

Genius 4925 points

In your code you have to set the Vcore to the maximum level using SetVcoreUp (or an equivalent).

Where is the example code from TI hanging?

In my current project I'm also using 25MHz as main clock, my initialization looks like this:

void setupDCO(void)
{

      /* Power settings */
      SetVCoreUp(1u);
      SetVCoreUp(2u);
      SetVCoreUp(3u);

      UCSCTL3 = SELREF__REFOCLK;    // select REFO as FLL source
      UCSCTL6 = XT1OFF | XT2OFF;    // turn off XT1 and XT2

      /* Initialize DCO to 25.00MHz */
      __bis_SR_register(SCG0);                  // Disable the FLL control loop
      UCSCTL0 = 0x0000u;                        // Set lowest possible DCOx, MODx
      UCSCTL1 = DCORSEL_6;                      // Set RSELx for DCO = 50 MHz
      UCSCTL2 = 762u;                            // Set DCO Multiplier for 25MHz
                                                // (N + 1) * FLLRef = Fdco
                                                // (762 + 1) * 32768 = 25.00MHz
      UCSCTL4 = SELA__REFOCLK | SELS__DCOCLK | SELM__DCOCLK;
      __bic_SR_register(SCG0);                  // Enable the FLL control loop

      // Worst-case settling time for the DCO when the DCO range bits have been
      // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
      // UG for optimization.
      // 32*32*25MHz/32768Hz = 781250 = MCLK cycles for DCO to settle
      __delay_cycles(781250u);

      /* Loop until XT1,XT2 & DCO fault flag is cleared */
      do
      {
        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                                // Clear XT2,XT1,DCO fault flags
        SFRIFG1 &= ~OFIFG;                      // Clear fault flags
      }
      while (SFRIFG1&OFIFG);                    // Test oscillator fault flag

}

void SetVCoreUp (unsigned int level)
{
    // Open PMM registers for write access
    PMMCTL0_H = 0xA5;
    // Set SVS/SVM high side new level
    SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
    // Set SVM low side to new level
    SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
    // Wait till SVM is settled
    while ((PMMIFG & SVSMLDLYIFG) == 0);
    // Clear already set flags
    PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
    // Set VCore to new level
    PMMCTL0_L = PMMCOREV0 * level;
    // Wait till new level reached
    if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
    // Set SVS/SVM low side to new level
    SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
    // Lock PMM registers for write access
    PMMCTL0_H = 0x00;
}

Okay in my project I'm using an external crystal as source, but I changed it a bit to use REFO-Clk. Works fine for me.

0 Jens-Michael Gross over 13 years ago

Guru 227245 points

Vinoth S said:
We required to run the clock at the maximum speed supported by the controller 25MHZ

Excet for a few lucky cases, you simply cannot run the CPU from 25MHz DCO.

The reason is simple: the DCO only has a small number of distinct frequencies it can produce. There are only a few 100s (depends on clock module/MSP family) from soem kHz to >100Mhz.. Chances are, that 25.0MHz is none of them.
To allow some more than these few frequencies, teh DCO operates in modulate mode. That means it produces a pattern of some clock pulses of the next lower frequency and some clock pulses of the next higher.
Unfortunately, to be on the safe side, none of the clock pulses is allowed to be >25Mhz (<40ns). So if not per pure coincidence 25MHz is one of the frequencies the DCO can directly produce (and won't exceed with temperature drift), it cannot average between two to get 25MHz average.

For a specific MSP (don't remember the device nr) I once calculated that for worst case and taking all min/max tolerances into account, the maximum safe frequency one can get with the DCO is slightly above 23MHz. Then it will be guaranteed (by the datasheet) that the upper frequency used for averaging does not exceed 25MHz.

However, why don't you use a crystal? Sure, it requires some more power than the DCO (but not so much, as you can disable the DCO and the FLL then), but you'll get stable 25MHz and no clock jitter. And do not need to calibrate each device.

**Attention** This is a public forum

MSP low-power microcontrollers

MSP low-power microcontroller forum

MSP430F5529 Clock Configuration for 25Mhz