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MSP430F5659: PORT26 errata

Viktorija Cecil
Mastermind 18501 points
Part Number: MSP430F5659


Tool/software:

Team, 

Can you please help answer my customer's question below:

We use P1.1 and P1.2 as inputs in our application. P1.1 is used as internal pull-down and P1.2 is used as internal pull-up.

In order to implement the workaround 1-a (per above errata screen shot), I am planning to make both P1.1 and P1.2 as output LOW during boot-up process and when its time to initialize GPIO, I will configure them as needed in our application (P1.1 as i/p PD, P1.2 as i/p PU).

My question is – What is the minimum time needed to keep these two pins as o/p LOW so that workaround 1-a works seamlessly. I did not find this information on errata (or any other TI’s documentation).

Thanks

Viktorija

  • 0
    TI__Mastermind 26410 points

    Hi Viktorija,

    We don't have a set amount of time but I believe that setting it output low then setting the IO to the input with internal resistors how you want after would be enough time. The IO simply needs to see 0 state before being able to correctly read the pins.

    If it doesn't work then you may need to add a couple of clock cycles to allow any capacitance to dissipate. 

    Regards,
    Luke

  • 0
    Guru 24865 points

    The errata specifically says an external pull up. So it wouldn't seem to apply when using the internal pullup.

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