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ADC12 Sample and hold time.

Steven Gan Teck Yik
Expert 1220 points


Hi guys,
May I ask what is the function of the ADC12 sample and hold time (ADC12SHT1 and ADC12SHT0)? Do explain how do we choose the value for it.
Is it the more sample and hold time the more accurate our ADC result?

  • 0
    Genius 4925 points

    You can think of the analog input stage of the ADC as being a RC-lowpass. Depending on your input resistance it will take more or less time to charge the sample capacitor to the actual voltage you sample. Basically you want to wait until you have charged the capacitor to within a level of 1/2 LSB that is (1-(1/4096)/2 = 0.9998779296875), now using some basic electrical engineering calculations you can come up with the needed time. Or you just take the formulas given in the user guides (it's in the ADC12 section).

    General rule: high impedance source - longer sample time, low impedance source - shorter sample time. If you need a short sample time consider using an external voltage follower.

  • 0 in reply to Bernhard Weller
    Expert 1220 points

    Bernhard Weller said:

    You can think of the analog input stage of the ADC as being a RC-lowpass. Depending on your input resistance it will take more or less time to charge the sample capacitor to the actual voltage you sample. Basically you want to wait until you have charged the capacitor to within a level of 1/2 LSB that is (1-(1/4096)/2 = 0.9998779296875), now using some basic electrical engineering calculations you can come up with the needed time. Or you just take the formulas given in the user guides (it's in the ADC12 section).

    General rule: high impedance source - longer sample time, low impedance source - shorter sample time. If you need a short sample time consider using an external voltage follower.

    OK.

    The sample formula from the ADC12 section of datasheet is as below:

    tsample > (Rs + 2k Ohm) x 9.011 x 40pF + 800ns

    Rs is the external resistance. If Rs = 10K, tsample > 5.13us. Does this means that the ADC will sample one time in 5.13us?

    What is the relationship of this value with the sample and hold time? If tsample > 5.13us, what is the value we should put for the ADC12SHT0 register?

    If the Rs is not fix like sometimes 10K, sometimes 1K or sometimes 50K or just 250 ohm. How do we choose the sample and hold time?

     

  • 0 in reply to Steven Gan Teck Yik
    Genius 4925 points

    Well your ADC samples in the time given by the SHT registers, which define an amount of clock cycles it waits. So if you select 256, it will wait 256 clock cycles and then start the conversion.

    To get your settings right, you basically have to make a worst case analysis. That means, you have to take the highest clock frequency of the ADC clock, and the highest external resistance. If it is 50kOhm, then take this and f you use ADCOSC the maximum frequency might be 5.4MHz. So with that you will get a needed sample time of 19.54288µs now just multiply this with the ADC clock frequency to get the cycle count which will give you 105,531552.

    Now you could select 128 clock cycles, or to accommodate for tolerances, temperature dependence of the resistance and other things maybe 192 or 256 cycles to be on the safe side.

    Note that this basically limits the frequency at which you are able to sample your signal. If you need to sample your signal at a higher frequency (it would be limited now to ~15-30kHz = (1/((sample cycles + 13 conversion cycles) /minimum ADC clock frequency)) ) you have to reduce your input resistance using a buffer (e.g. unity gain operational amplifier).

    Edit: changed minimum input frequency to minimum ADC clock frequency to be less ambiguous

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