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MSP430F6775A: BOOT

Peter Peter
Intellectual 400 points

Part Number: MSP430F6775A

Tool/software:

Hi,

I would like to ask, If  I store values from any register like module in the start of main program  or in system_pre_init() funtion into an array shouldn't be the value the same as default defined in the user guide? I mean the default configuration loaded by the bootcode in the hidden partition should match the stored configuration or not? If I did not modified any register yet of course. And also may be the configuration read from that location different than what debugger says during debugging when jtag is used? I don't mean the registers which are used by the debuging module. I mean I did so and in some cases they are different like the FLLD part of UCS seems to have a zero there instead of one which should be default according to UG. And I am wondering what could be wrong.

Thank you for your answer. 

  • 0
    TI__Mastermind 23497 points

    Hi, 

    Can you show me your detailed register read postion?

    Also, please try add some delay to read the register~

    Regards,

    Helic

  • 0 in reply to Helic Chi
    Intellectual 400 points

     Address = 0x0164 Data = 0x001F

    |------------------------------------------|
    | UCSCTL2
    |------------------------------------------|

    |------------------------------------------|
    | Field       DEF  DEF    NEW |
    |------------------------------------------|
    | FLLNx1 | rw-1 | | 1 | | 1 |
    |------------------------------------------|
    | FLLNx2 | rw-1 | | 1 | | 1 |
    |------------------------------------------|
    | FLLNx3 | rw-1 | | 1 | | 1 |
    |------------------------------------------|
    | FLLNx4 | rw-1 | | 1 | | 1 |
    |------------------------------------------|
    | FLLNx5 | rw-1 | | 1 | | 1 |
    |------------------------------------------|
    | FLLNx6 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | FLLNx7 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | FLLNx8 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | FLLNx9 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | FLLNx10 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | RESERVED0 | r0 | | 0 | | 0 |
    |------------------------------------------|
    | RESERVED1 | r0 | | 0 | | 0 |
    |------------------------------------------|
    | FLLDx1 | rw-1 | | 1 | | 0 | ***
    |------------------------------------------|
    | FLLDx2 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | FLLDx3 | rw-0 | | 0 | | 0 |
    |------------------------------------------|
    | RESERVED2 | r0 | | 0 | | 0 |
    |------------------------------------------|

    Here is detailed redout from that register in the position labled with *** there was difference between default value and actual value there already was delay 50000 cycles and it was the same each time. First is the register field name than defaut value with access permition than just default value as whole number and than in the last column the actual value under the "NEW " lable.

  • 0 in reply to Peter Peter
    TI__Mastermind 23497 points

    Hi, 

    Peter Peter said:
    it was the same each time

    Both set PC to start or power on reset device read is wrong at mark ***?

    What function do you want to achieve?

    Seems this register can be configured during init, and won't influence the device's function.

    If there are more information, I can give you some advice~

    Regards,

    Helic

  • 0 in reply to Helic Chi
    Intellectual 400 points

    Hi,

    This function was called in main function after device was reset right after WDT was hold. But I also called it in the _system_pre_init and the bits in that configuration were same. Well the main functionality is to check the register values before and after configuration and also before and after reset cuz I cannot check it in the free run  without setting breakpoint so it is used as additional verification tool. Yes the *** signalizes that the configuration of register is different when compared to default configuration. 

  • 0 in reply to Peter Peter
    TI__Mastermind 23497 points

    Hi, 

    From my point of view, depending on this register's function, PLLD should be 0x00.

    If this won't influence any function in your software, you can treat it as 0x00 in default.

    Regards,

    Helic

  • 0 in reply to Helic Chi
    Intellectual 400 points

    Hi,

    It just does not make any sense to me when I do the debug with breakpoint than it is set so I am a little bit confused about which one is correct.

  • 0 in reply to Helic Chi
    Intellectual 400 points

    And it was FLLDx1 which I was interested in.

  • 0 in reply to Helic Chi
    Intellectual 400 points

    I have noticed that I have pointed to just one byte of memory so thats why it was not set so I am sorry. The FLLDx1 bit is set but, there are some reserved bits in UCSCTL7 thet are reset. I would like to ask should I take that on mind and also the mod and dco bits? 

  • 0 in reply to Peter Peter
    TI__Mastermind 23497 points

    Hi, 

    You can ignore some reserve bit in UCSCTL7~ depending on TRM 5.4.8 UCSCTL7 Register

    For CTL0, these bits are modified automatically during FLL operation.

    Regards,

    Helic

  • 0 in reply to Helic Chi
    Intellectual 400 points

    Hi,

    What is TRM?

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