MSP430F5132 Clock Stability Issue

The DCO is controlled through REFO by an FLL, a frequency-locked-loop.
Basically, teh FLL is counting the numbe rof DCO pulses between two reference pulses and adjusts the DCO according to the result.
Unfortunately, the DCO adjustment happens in rather rough steps (up to 12%), and the modulation feature jsut smoothes this a bit by switchign between two DCO steps on a defineable pattern.
On the bottom line, the DCO-generated clock will have a large clock jitter between two single clock pulses and also changes the frequency every now and then.
The formula f_DCO=f_REFO*factor i sonly true for the average frequency over a longer time period.

If your measurement equipment just measures the time between two clock pulses, it will show large variation between two measurement, depending on which pulse is coincidentally picked form the pattern.

If you measure the frequency by counting the clock ticks during a certain interval, you'll get much more 'expected' results, more or less matching the REFO precision.

You can disable modulation. This will eliminate thepulse-to-pulse jitter, but limit the number of 'adjustment steps' of the FLL to a few hundred frequencies. Most certainly none of them being the one you want. So you have no jitter but a heavy skew that is positive or negative depending on the FLL regulation (changes direction on every adjustment cycle). Giving the wanted frequency in the average.
Or you disable the FLL. This will remove the skew but not the jitter and won't give exactly the wanted frequency, not even as average..
Or you disable both, giving you a jitter-free clock with a constant skew (except for temperature drift) but even less the wanted frequency.

However, a precise and stable and jitter-free clock can only be generated by using a crystal.

We have disabled the FLL.

 

Jitter of REFO is much greater than REFO frequency voltage drift from the F5132 datasheet, 1.0% per volt.

 

Jitter of DCO is much greater than DCO frequency voltage drift from the F5132 datasheet, 1.9% per volt.

 

Our assumption was that jitter would be less than frequency voltage drift.

 

With significant jitter, neither REFO nor DCO can be used as timebases for UART serial communications.  Clock frequency changes too much within / between communicated bytes.

 

Is any data available regarding jitter of either of these 2 clocks?

 

Is there anything that can be done, either in hardware or firmware, to reduce the jitter of these clocks?

 

Good supply regulation seems to reduce jitter.  On which supply pins of the F5132 should bypassing be maximized to reduce jitter?

Thanks Jens-Michael.

Arrow Vancouver said:

We have disabled the FLL.

You know, without FLL, REFO has no influence on the DCO. (well, I guess you disabled it after the FLL has settled DCO)

Arrow Vancouver said:

Jitter of REFO is much greater than REFO frequency voltage drift from the F5132 datasheet, 1.0% per volt.

I'm surprised that REFO has a jitter at all. It shouldn't. Are you sure it isn't jsut a variation in duty cycle (so the jitter disappears when comparing the othe redge)?

Arrow Vancouver said:

Jitter of DCO is much greater than DCO frequency voltage drift from the F5132 datasheet, 1.9% per volt.

DCO jitter is caused by modulation, as the modulation feature switches between two DCO frequencies for an average result. The jitter can be as high as 12%.
However, if modulation is disabled, there should be no jitter at all. The DCO is an R/C oscillator with digital control. If no tap switching occurs, the resulting frequency should be jitter-free.

Arrow Vancouver said:

Good supply regulation seems to reduce jitter. 

Well, if the frequency voltage drift is 1%/V and you have much ripples on your supply, then this indeed can cause a 'jitter' which is just a voltage drift following the supply ripple.

Do you have the required capacitance on the VCore pin (and no crosstalk from VCC to VCore)? It will help to reduce the voltage ripple on VCC caused by CPU operation.
For DVCC/DVSS decoupling, you should spread the total decoupling capacitance over all pins equally. And use not the cheapest capacitors as tehy usually have a high ESR. Additional small ceramic capacitors do help too. And keep the connections short. Especially for VCore capacitors.
(we once had a layouter who placed all decoupling capacitors into one corner of the layout - of course he had to redo the whole thing before we ordered a PCB)