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MSP430FR6043: ADC Conversion Time

Part Number: MSP430FR6043


Tool/software:

Hi,

I want to know about the ADC12_B conversion time formula. I am using 3 ADC channels A8,A9 and A14.

/***** adc hw setup ******/
adc_init.clockSourceSelect = ADC12_B_CLOCKSOURCE_ADC12OSC;
adc_init.clockSourceDivider = ADC12_B_CLOCKDIVIDER_1;
adc_init.clockSourcePredivider = ADC12_B_CLOCKPREDIVIDER__32;
adc_init.internalChannelMap = ADC12_B_NOINTCH;
adc_init.sampleHoldSignalSourceSelect = ADC12_B_SAMPLEHOLDSOURCE_SC;

/***** adc sampling timer ******/
ADC12_B_setupSamplingTimer(ADC12_B_BASE, ADC12_B_CYCLEHOLD_192_CYCLES,
ADC12_B_CYCLEHOLD_4_CYCLES,
ADC12_B_MULTIPLESAMPLESENABLE);

/***** start conversion ******/
ADC12_B_startConversion(ADC12_B_BASE, ADC12_B_START_AT_ADC12MEM0,
ADC12_B_REPEATED_SEQOFCHANNELS);

Regards,

SaKhan

  • ADC12OSC is 4.8MHz (nom.), so dividing by (1*32) gives an ADCCLK tick of 6.67usec. Each (12-bit) conversion takes (192+13+1) ticks, or 1373.3usec. 3x of them would be 4120usec. (With CONSEQ=3/MSC=1 there would be no pause between.)

    ADC12OSC is +/-12%, so don't count too much on that. There's no mention of VRSEL, so I'm supposing it's =0 (AVCC) i.e. no VREF startup time.

  • I am using ref_A module 2.0V as reference voltage. Could you please give me a formula or something. the above explanation bit confusing for me.

  • The formula I described above would be "(SHT0+13+1)*(PDIV*DIV)/Fadcclk" where (from your code) SHT0=192, PDIV=32, DIV=1, Fadcclk=Fadcosc=~4.8MHz. Then *3 for 3x channels.

    If you're setting REFON=1 in the REFA (Ref_A_enableReferenceVoltage), it's on all the time. If not: The wording in the UG is ambiguous (definition of the word "actively"), but I suspect that when running the ADC continuously (CONSEQ=3/MSC=1) it's always on anyway. Turning REFA off/on takes about 40usec (typical). 

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