MSP430FR2476: MSP430FR2476TPT

Supposing SMCLK=8MHz, you would want a period of (8MHz/4850)=1649.485. You would have to choose 1649 or 1650, which would give you 4851.4Hz or 4848.5Hz (respectively), an error of +/-1.5Hz. This is an error of +/-0.03%  (309ppm). 

The REFOCLK is only rated to +/-3% (30000 ppm), which would swamp this, so you would want to use a 32kHz crystal, where 20ppm is not difficult to find.

Hi Bruce McKenney,

Thanks for clarifying, our case we are using external 32.768kHz crystal with below attached specifications  

20ppm is small compared to the error you would see due to the integer divisor (CCR0). What is your SMCLK? Different SMCLK settings will produce different roundoff errors.

You may also see a small error due to the integer FLLN; 10 bits suggests about 98ppm.

What results do you see?

The micro is derived using the external 32K crystal. it is then converted to be 4MHz using the PLL. the 4MHz has jitter on it. need the micro spec for pll freq conversion tolerances

this means we can only have a mean PRI and PW. If i want it to be accurate then it will require a design change?

Some of the jitter might be coming from the modulator. You could try setting CSCTL1:DISMOD=1.

[Edit: Fixed typo.]

as per datasheet is it 10% tolerance for internal SMCLK?

I'm not quite sure what your question is.

1) The "+/-10%" here refers to a Duty Cycle requirement (input tolerance), which I suppose applies to internal as well as external clocks.

2) Sec 8.12.3.2 ("DCO FLL") does seem to say that the FLL output (including SMCLK) Duty Cycle can be +/-10%. I'm not sure where this variation would come from, or whether it would appear as skew or jitter.

3) I expect that Duty Cycle refers to the falling edge; the timer operates from the rising edge [Ref User Guide (SLAU445I) Sec 13.2.1].

4) Is there a concern about Duty Cycle? Thus far I've been talking about Frequency.

1) The "+/-10%" here refers to a Duty Cycle requirement (input tolerance), which I suppose applies to internal as well as external clocks.

Y: If i need 4.85KHz frequency from P4.0/TA3.1 Pin33 with 2% positive duty cycle what is the minimum frequency and duty cycle tolerance we get from this MCU

2) Sec 8.12.3.2 ("DCO FLL") does seem to say that the FLL output (including SMCLK) Duty Cycle can be +/-10%. I'm not sure where this variation would come from, or whether it would appear as skew or jitter.

Y: looking for how much tolerance will this MCU can produce at pin output for frequency and duty cycle.

3) I expect that Duty Cycle refers to the falling edge; the timer operates from the rising edge [Ref User Guide (SLAU445I) Sec 13.2.1].

Y: yes agree

4) Is there a concern about Duty Cycle? Thus far I've been talking about Frequency.

Y: both duty cycle and Frequency tolerance on the output side of the MCU P4.0/TA3.1 Pin33

The duty cycle resolution would be 4850/4MHz or 1/824.74. Choosing 825 provides a duty cycle resolution of 0.12%, or about 5.9Hz.

All the other considerations would be the same. Again: I don't think the duty cycle of the clock (proper) matters, since the timer uses only the rising edge.

What are your requirements? There exist very high quality clock chips (I think TI sells some) if that's what you really need.

[Edit: Minor clarification.]