MSP430FR5994: Msp430FR5994 UART TX port doesn't work

Tool/software:

Hello everyone.
I need a help about Msp430FR5994 Uart communication ports.
I'm trying to use msp430FR5994 (64 pins) to communicate with another device trough RS232. I've used a TRS3232E to permit communication between mcu and device. I've initialized
USCI_A2 for port P5.4 (TX pin 53) and P5.5 (RX pin 54), 112500 baud rate. Everything work fine for RX, nothing for TX. I've thought it was a hardware problem (pins, connections, TRS3232, mcu) : nothing.
I've also changed the pcb board, but I find the same problem. Using CCS for step by step debugging I've seen that TX registers and flags seems to work properly,
but it seems like the port P5.4 is not open. I've tried to use two example codes from TI modifing them for my porpouses and to see if TX port works properly:
the Echo betweem PC and mcu, and the Echo with TX and Rx ports shorted.Unfortunately I find the same problems.

You'll see my codes below. Could someone please help me?
I've been racking my brains for days without finding a solution. Where did I go wrong? What have I missed? Thanks in advance

//Echo PC mcu
#include <msp430.h>

int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop Watchdog
PM5CTL0 &= ~LOCKLPM5;
// Startup clock system with max DCO setting ~8MHz
CSCTL0_H = CSKEY >> 8; // Unlock clock registers
CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 8MHz
CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers
CSCTL0_H = 0; // Lock CS registers
UCA2CTLW0 |=UCSWRST; // Put eUSCI in reset
UCA2CTLW0 |= UCSSEL__SMCLK; // CLK = SMCLK
UCA2BR0 = 4;//prima 52;
UCA2MCTLW|= UCOS16 | UCBRF_5 ;
UCA2MCTLW|= 0x5500;
// **Configure P5 port per UART
P5SEL1 |= (BIT4 | BIT5); // USCI_A2 UART operation
P5SEL0 &= ~(BIT4 | BIT5);
UCA2CTLW0 &= ~UCSWRST;
UCA2IE |= UCRXIE;
__bis_SR_register( GIE );

while( 1 )
{
_NOP();
}
}

#pragma vector=USCI_A2_VECTOR
__interrupt void USCI_A2_ISR(void)

{
switch(__even_in_range(UCA2IV, USCI_UART_UCTXCPTIFG))
{
case USCI_NONE: break;
case USCI_UART_UCRXIFG:
while(!(UCA2IFG&UCTXIFG));
UCA2TXBUF = UCA2RXBUF;
_NOP();
break;
case USCI_UART_UCTXIFG:
break;
case USCI_UART_UCSTTIFG: break;
case USCI_UART_UCTXCPTIFG: break;
}
}

//*******************************************************************
//****Echo with tx-rx ports shorted
#include <msp430.h>

volatile unsigned char RXData = 0;
volatile unsigned char TXData = 1;

int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop Watchdog
// **Configure P5 port per UART
P5SEL1 |= (BIT4 | BIT5); // USCI_A2 UART operation
P5SEL0 &= ~(BIT4 | BIT5);

PM5CTL0 &= ~LOCKLPM5;
// Startup clock system with max DCO setting ~8MHz
CSCTL0_H = CSKEY >> 8; // Unlock clock registers
CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 8MHz
CSCTL2 = SELA__VLOCLK | SELS__DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers
CSCTL0_H = 0; // Lock CS registers

UCA2CTLW0 |=UCSWRST; // Put eUSCI in reset
UCA2CTL1 |= UCSSEL__SMCLK; //prima UCA2CTLW0 |= UCSSEL__SMCLK;
UCA2BR0 = 4;
UCA2MCTLW|= UCOS16 | UCBRF_5 ;
UCA2MCTLW|= 0x5500;
UCA2CTLW0 &= ~UCSWRST; // Initialize eUSCI
UCA2IE |= UCRXIE; // Enable USCI_A2 RX interrupt

while (1)
{
while(!(UCA2IFG & UCTXIFG));
UCA2TXBUF = TXData; // Load data onto buffer

__bis_SR_register(LPM0_bits | GIE); // Enter LPM0, interrupts enabled
}

}

#pragma vector=USCI_A2_VECTOR
__interrupt void USCI_A2_ISR(void)

{
switch(__even_in_range(UCA2IV, USCI_UART_UCTXCPTIFG))
{
case USCI_NONE: break;
case USCI_UART_UCRXIFG:
RXData = UCA0RXBUF; // Read buffer
__bic_SR_register_on_exit(LPM0_bits); // Exit LPM0 on reti
break;
case USCI_UART_UCTXIFG: break;
case USCI_UART_UCSTTIFG: break;
case USCI_UART_UCTXCPTIFG: break;
}
}