Problems with timing scheme

}Hi Ernesto, set adc12 to start conversion on TAx then enable inerrupt of timerA channel X

Init TACCRx to fire first sample when appropriate or with just some delay

...

setup timer

enable interrupt.

setup ca[ture at some delay after now:

TACCRx=TAR+yy; // yy can be a fixed number of tick to fire after actual TAR counter register

 On interrupt service do this:

if(nsamples<50)

{

if(nsamples&1)

 TACCRx+=(t0-td);

else

 TACCRx+=t0;

nsamples++;

}

else

 {

 nsamples=0;

 stop counter capture on this channel

}

 I hope you can start from here

Regards

Roberto

Thanks for your reply. As you mention, t0 can be divided by td so I'm implementing this now. I just wondered how to implement the timing I need taking only the relevant samples. 

By the way, in the user guide I've seen that SHI can be triggered from TA1 and TB1. Is is possible to synchronize TA and TB so they generate the timing I need? I'm thinking on a scheme like this:

*Initialize both timers to two different values

*TA1 triggers conversion

*At the end of conversion, change ADC12 setup so it is now triggered by TB1

*TB1 triggers conversion

*At the end of conversion, change ADC12 setup again to TA1 trigger

*repeat as many times as needed

Can you think on any issues with this algorithm?

Thanks for your suggestion, Roberto. I didn't explain that my application needs t0 to be about 100 microseconds, and I'm afraid that changing TACCRx on each ISR will make the timing "drift", increasing on each consecutive sample because the CPU won't be fast enough to execut ISR. For example, if the instructions to change TACCRx are executed in say 0.1 microseconds then after 50 samples the total drift would be 5 microseconds yielding an error of 5 % respect of t0. Do you think that I might be overestimating execution time? I'm really clueless about this.

 Hi Ernesto, Limit come from ADC 5uS conversion time, CPU handle interrupt frequency of 100Khz but @ low budget inside, in your case 100uS->10KHz  you have space to 800  cpu cycles, no problem to serve this timing scheme.

 Problems can arise on td, if td is less than 5uS ADC is again unusable and also time to fire next sample can be too close, if this is your case program adc to do multiple conversion and get result from two or more channel. If td is so close wait it firing into IRQ service (Bad but no other solution) then clear irq and refire for next To slot. Using register variable can also help speedup calculations.

 Please be more precise on what you want and specify all timing scheme.

 Regards

 Roberto

Ernesto Serrano said:

*TA1 triggers conversion

*At the end of conversion, change ADC12 setup so it is now triggered by TB1

*TB1 triggers conversion

*At the end of conversion, change ADC12 setup again to TA1 trigger

*repeat as many times as needed

Can you think on any issues with this algorithm?

 Yes, you use two independent timers so TAR and TBR not necessarily are aligned, IRQ service burden more cpu than simply recalculate where is next sample.

 I hope your understanding on how Timer work are false, so there is a free run counter TAR where you set the compare point where interrupt and external event are to be fired.

 So in your other post you are speaking about drift, drift is from your code not from timer timer forever are locked to TAR and slot precisely fire after the number of tick you program in TACCRx.

 In example:

 TAR = 10

 TACCRX =110

 interrrupt is fired after 100 TAR tick when TAR is 110 (how fast tick are depend on where you clocked it.)

 TACCRx+=52

  interrupt is fired after 52 tick when TAR is 110+52->162

 TACCRx+=48

  interrupt is fired after 48 tick When TAR is 162+48->210

 I Hope this can clear your understanding of how timer work.

 MSP CPU is RISC horthogonal instruction so is fast and code efficient, one  c line assemble to 1.5 average assembly instruction so don't be scary by power. If cpu run too much time and still need battery powered appliance select  more fast unit, leave it in LPM then execute code at fastest speed.

 Regards

 Roberto

The main problem with more than one timer, or a increasign time rinterval, is not the alignment or that critical timing.
The main problem is that the trigger for the ADC needs to be a pulse. A full transition from low to high and back. A CCR event alone does only alter (at best) the CCR unit output signal.

It is the 'reset' at the tiemr overflow on the given period that will complete the cycle and arm the CCR for the next compare event.

Basically, you're generatign a PWM output where the rising edge controls the moment of conversion start. Or, with SHP clear) the rising edge opens the inptu and the falling edge starts the conversion.

However, you cannot just increment the CCR value for the next event, or switch the ADC to a different timer source. The outcome is more or less unpredictable. But definitely not what you want.
For incrementing the CCR value, you'll need to use the toggle output mode and you require twice the CCR event frequency as you want. And for two timers, well, a lot of synchronizing is required.

From code view, taking excess samples and then just pick teh 1st, 3rd, nth (according to the pattern) is the easiest, fastest and cleanest way. It does, however, require some buffer memory if you want to take all samples first and pick them. Or you trigger an ISR after each conversion and decide whether to keep the sample or drop it.