Part Number: LP-MSPM0G3507
Tool/software:
Hi,
I'm currently developing a UART application on the MSPM0 using DMA for RX data handling. I've encountered a behavior that seems inconsistent with the description in the Technical Reference Manual.
According to the MSPM0 Technical Reference Manual (TRM), the receive interrupt (RXINT) is cleared when the number of entries in the RX FIFO becomes less than the trigger level. DMA should transfer only enough data to reduce the FIFO level just below the threshold.
However, during UART + DMA development, I observed that under specific conditions, DMA drains the entire FIFO.
I enabled the FIFO, set the RX FIFO Threshold Level to RX FIFO contains>= 2 entries and set the DMA Transfer Mode to Single.
When I send two bytes to the serial port, one byte should be transferred from RXFIFO to DestAddr, leaving one byte in RXFIFO. But I found that both bytes get transferred.
When I send three bytes to the serial port, two bytes are transferred and one byte is kept.
When I send four bytes to the serial port, it transfers all four bytes.
Then I change the RX FIFO Threshold Level to RX FIFO contains>= 3 entries.
Send 3 bytes → All 3 transferred
Send 4 bytes → 3 transferred, 1 remains
Send 5 bytes → 3 transferred, 2 remain
Send 6 bytes → All 6 transferred
Overall, when the number of received bytes is an exact multiple of the threshold, the DMA unexpectedly drains the FIFO completely, which contradicts the TRM’s description. In contrast, non-multiples behave as expected. Only the minimum number of bytes is transferred to clear RXINT.
Is this behavior expected by design? If not, is there an erratum or workaround?
Thank you!
This is the project I used for testing:
