Part Number: MSP430FR6043
Tool/software:
We have a custom board running the MSP430FR6043 based on the demo library.
We have programmed hundreds of boards successfully, but we have a few that get hung up in the ultrasonic routine. We are trying to figure out what part of the hardware is not functioning correctly.
Several boards fail in the following code. In this case the UPSTATE_3 bit of the UUPSCTL register never gets set, causing the watchdog timer to fire. The actual failure occurs on this line :
// Wait until USS module is in READY state
while((UUPSCTL & UPSTATE_3) != UPSTATE_3);
What inputs to the TMS430FR6043 could cause this failure ? Also where can we find a definition / description of the UPSTATE_3 bit ? How else can we troubleshoot the hardware side of this?
Here is a large code snippet of the section.
#pragma vector= USSLIB_HAL_TIMER_RXEN_CCR1_VECTOR
__interrupt void USSLIB_HAL_TIMER_RXEN_INT(void)
{
switch(__even_in_range(HARDWAREWREG16(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS
+ OFS_TAxIV),
TAIV__TAIFG))
{
case TAIV__NONE: break; // No interrupt
case TAIV__TACCR1: // CCR1, Enables RXEN
// Enable RxEN, RxEN will be turned Off after USS
acquisition
USSSWLIB_HAL_AFE_RXEN_PORT |= (USSSWLIB_HAL_AFE_RXEN_PIN);
// Disable Timer
HARDWAREWREG16(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS +
OFS_TAxCTL) &= ~(MC_3 | TAIFG);
break;
case TAIV__TACCR2: // CCR2, start ASQ, restart timer
to trigger RxEN
// Wait until USS module is in READY state
while((UUPSCTL & UPSTATE_3) != UPSTATE_3);
// Stop timer
HARDWAREWREG16(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS +
OFS_TAxCTL) &= ~(MC_3 | TAIFG);
// Disable CCR2 interrupt
HARDWAREWREG16(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS +
OFS_TAxCCTL2) = 0x00;
// Enable CCR1 interrupt to enable RxEN
HARDWAREWREG16(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS +
OFS_TAxCCTL1) = CCIE;
// Restart timer
HARDWAREWREG16(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS +
OFS_TAxCTL) |= ( TACLR | MC__CONTINOUS);
// Trigger ASQ
GENERIC_SAPH_ASQTRIG = ASQTRIG;
break;
case TAIV__TACCR3: break; // reserved
case TAIV__TACCR4: break; // reserved
case TAIV__TACCR5: break; // reserved
case TAIV__TACCR6: break; // reserved
case TAIV__TAIFG: break; // overflow
default: break;
}
}
