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msp430f5438a timer isr vector swap

Steven Arroyo
Prodigy 80 points
Other Parts Discussed in Thread: MSP430F5438A

I have been working with the MSP430f5438a timer blocks and have ran into some strange behavior.  I am pretty certain I have found the root cause.  It seems that the ISR vector for timer A0 CCR1-6  and Timer A1 CCR0 have been swapped.  The workaround I have found is modifying the msp430f5438a.h file as follows:

OLD:

#define TIMER1_A0_VECTOR        (49 * 1u)                    /* 0xFFE2 Timer1_A3 CC0 */
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int49")  */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */
.......

#define TIMER0_A1_VECTOR        (53 * 1u)                    /* 0xFFEA Timer0_A5 CC1-4, TA */
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int53")  */ /* 0xFFEA Timer0_A5 CC1-4, TA */ /* CCE V2 Style */


FIX:



#define TIMER1_A0_VECTOR       (53 * 1u)                  /* 0xFFE2 Timer1_A3 CC0 */
/*#define TIMER1_A0_ISR(func)     ISR_VECTOR(func, ".int49")  */ /* 0xFFE2 Timer1_A3 CC0 */ /* CCE V2 Style */


.......



#define TIMER0_A1_VECTOR        (49 * 1u)                   /* 0xFFEA Timer0_A5 CC1-4, TA */
/*#define TIMER0_A1_ISR(func)     ISR_VECTOR(func, ".int53")  */ /* 0xFFEA Timer0_A5 CC1-4, TA */ /* CCE V2 Style */






Timers now work as expected.  I did not see any mention of this in the device errata.  If I am missing something please let me know the correct fix.




Thanks,
Steven 

								


				
				

				
			

		

			
						
									
                			    			                        
						
						
			
			
						
			                        
			
			
				
			  
			

			     
			

		


				    			

						
















	

	

					
    
	
    





		
	
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                          Guru
                        58965 points
                      
    
                          
                   		
		
    
					
    I think you may have been misled by TI terminology or "naming convention". 

I do not think they swapped the value of the two in the HEADER file. I think they made you to swap the meaning of the two in your HEAD.

The MSP430F5438a chip has 3 separate and independent Timers. One with 5 capture/compare registers, one with 3, and another one with 7. These 3 Timers may generate 1+1+1=3 different Timer Overflow Interrupts, and also  5+3+7=15 different Capture/Compare Interrupts. Hence there are a total 3+15=18 different Timer related interrupts. 

Which Timer Interrupt(s) do you think will activate the ISR for Timer1_A0_VECTOR? 

Which Timer Interrupt(s) do you think will activate the ISR for Timer0_A1_VECTOR?
    
			
    

		
		
		
		
	
    
	
    
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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                          Guru
                        227245 points
                      
    
                          
                   		
		
    
					
    OCY is right, you misinterpreted the naming.
    

    The naming convention is:
    

    TIMERx_yz_VECTOR.
    

    Where y is the timer type, x is the number of the timer of this Type and z is the vector index.
    

    So TIMER1_A0_VECTOR and TIMER1_A1_VECTOR both belong to TIMER A1.
    

    It shoudl rather be TIMER_A1_VECTOR0 and TIEMR_A1_VECTOR1, but appending th evector index to the 'VECTOR'  appendix looked a bit ugly for the one who generated this.
    

    Originally, there was only one TIMER A at most, so the names have been TIMER_A0/TIMER_A1 for the two vectors. Btu when an index became necessary, it has been added after 'TIMER', making things more confusing than before.
    
			
    

		
		
		
		
	
    
	
    
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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