• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 80 subscribers
  • Views 246 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR2000: startup time from power off

Kenley
Intellectual 1805 points
Part Number: MSP430FR2000


Tool/software:

Hi team,

What is the startup time of the microcontroller equipped with FRAM?

From a power loss state, how quickly does it take to start power up post-processing?

I checked the data sheet of MSP430FR2000 as a test, and found that 1ms was written in typ. From BOR.

Is it difficult to recover power from a complete power loss by a few tens of μs?

Best regards,

Kenley

  • 0
    Guru 100965 points

    You probably won't get 10s of usec, but it may not be (quite) as bad as the datasheet says.

    I instrumented a program by wiggling a GPIO in __system_pre_init, and ran it on an FR2311 (Launchpad). I measured 440us from power ramp (3.0V) to the GPIO edge; probably 40-50usec of that was the code path from the Reset vector to my code. So maybe 400usec in "real life".

    The F2 series User Guide [SLAU144K Sec 2.1.1 and Fig 2-2] mentions a delay (tBOR) after the power ramp reaches the high-hysteresis level, before releasing reset. I think this is intended as a filter of sorts for noisy power supplies. It wasn't adjustable. The (e.g.) F2274 datasheet quotes tBOR as 2ms(!) max, but in practice it was much shorter.

    The FR2 series User Guide (SLAU445i) doesn't mention this delay (tBOR is something different there) but I wouldn't be surprised if it were there. 

  • 0 in reply to Bruce McKenney
    TI__Intellectual 1805 points

    Hi Bruce,

    thank you for the support!

    So do you mean 400μsec based on your test + the delay (tBOR) 2ms max. should be considered as the total startup time ?

    Best regards,

    Kenley

  • 0 in reply to Kenley
    Guru 100965 points

    The tBOR delay (if present in the FR2x) wouldn't be additive, rather part of the 400us I measured. I just offered tBOR as an example of the kind of internal startup activity one Might see between the SVS giving a go-ahead on power and executing the first instruction at the Reset vector. [Nobody gave me the keys to the Verilog, so I can only guess what actually happens.]

    The experiment was intended to suggest that you won't get startup in 10s of usec, but you probably won't see 1ms either.

  • 0
    TI__Intellectual 940 points

    Hello Kenley, 

    Hope you are having a good start to your day. Nevertheless, I wanted to check in with you if you are satisfied with the responses from Bruce and all's good. Also, feel free to keep us know if you have further questions or concerns. 

    Regards, Jojo

  • 0 in reply to JOJO ARTHUR
    TI__Intellectual 1805 points

    Hi Bruce and Jojo,

    Yes, thank you for the confirmation.

    I am satisified with the responses and waiting for customer's feedback right now.

    Thanks again for the support.

    Best regards,

    Kenley

  • 0 in reply to Kenley
    TI__Intellectual 940 points

    You are welcome Kenley. Feel free to reopen this thread if anything arises.

    Regards, Jojo

**Attention** This is a public forum