Other Parts Discussed in Thread: MSP-GANG
Tool/software:
Hi All,
Can you review the MSP430F5324 defect report and answer any questions?
[Defect Description]
・The microcomputer was MSP430F5324.
・A market product claim occurred.
As a result of reading the contents written in the defective microcomputer by BSL communication,
the contents of the memory were different from those of the normal product.
The difference is "00 00 is included in some parts and the value is off."
・The cause of the defect is known to be that the correct value was not written in the microcomputer.
・The occurrence rate is being checked.
[Result of checking defective products]
・When trying to verify the defective product by JTAG communication, communication was not possible because the JTAG lock was engaged.
・When trying to verify the defective product by BSL communication, a verify error occurred. (The written content is as described in the above defect content.)
・In the production line, writing errors occasionally occur when writing by JTAG communication.
However, when writing by JTAG again and it is normal, it is used in the product.
In mass production, writing by JTAG communication and if it is normal by verify, JTAG lock is applied.
[Question]
・Is it possible that a problem like this occurs other than writing?
I want to distinguish whether it occurs during microcomputer writing or after it is released to the market
(1) The product writes to Information Memory C and D to memorize settings.
Is it possible that an error occurs during the operation and 00 00 is entered and the value is shifted?
(2) Is it possible that external noise occurs in the product and 00 00 is written and the value is shifted?
(3) Is it possible that 00 00 is written and the value is shifted due to timing shift such as noise during microcomputer writing?
・If there is a movement of "00 00 is entered and the value is shifted partially" like this time in Verify when writing by JTAG communication during mass production,
(1) Can the content of the defective product read this time be detected by Verify of JTAG communication?
(2) Is there a possibility that Verify is recognized as normal by mistake? When can it occur?
From the Verify calculation, is it possible to judge that the Verify value is normal for the written content of this defective product?
・If it is written by JTAG communication at the time of mass production, is it correct that JTAG lock is not applied if Verify abnormality is shown?
Is it possible that JTAG lock is applied even if Verify abnormality is shown?
・Have you heard of such a problem with MSP-GANG? (Other companies, etc.)
・Is there any difference between "Verify with JTAG communication" and "Verify with BSL communication" with MSP-GANG?
(1) Is it possible that this problem is not noticed by Verify with JTAG communication but is noticed by Verify with BSL communication?
(2) Is there a way to perform full verify with JTAG communication of MSP-GANG?
(3) I understand that JTAG communication: PSA comparison, BSL communication: checksum +PSA comparison. Is it correct?
・I am trying to release JTAG lock using BSL communication of MSP-GANG, but I cannot release it.
I understood that it can be released by writing FF FF FF FF FF in memory of @17FC, but once JTAG lock is applied,
Is it possible to restore JTAG communication?
Regarding Memory Options when writing, "All Memory (without BSL sectors), including locked INFO-A"
I pressed Program button, but it was not changed when I read by Read and looked at @17FC.
[Our thoughts]
・I think the tool or power supply in the process of writing to the microcomputer is suspicious, but in that case, can it be detected by Verify? I think so.
・What happens to cause this phenomenon?
① From the content of the defect "00 00 is misplaced," I guessed that the value was likely misplaced when writing to the microcomputer.
However, isn't it possible to detect the abnormality by Verify performed when writing in JTAG communication? If so, isn't it possible that the defective product occurs?
② If Verify abnormality occurs in JTAG communication, it is possible that the erroneous content written in MSP-GANG remains in the microcomputer and causes an error.
However, if Verify abnormality occurs, JTAG lock should not be implemented.
Since JTAG lock was implemented this time, isn't it unlikely that Verify abnormality occurred but was overlooked and incorporated into the product?
⇒ Then, does it mean that Verify passed correctly?
After Verify was normal and JTAG lock was applied, 00 00 writing like this time occurred due to an external factor?
⇒ Or is it possible that JTAG lock is performed even if Verify does not pass correctly?
③ Verify passes correctly at the time of writing, but when Verify is performed later by BSL communication, an error occurs.
Is it possible that Verify becomes normal even if the value is wrong at the time of JTAG writing, and then when Verify is performed again by JTAG communication or BSL communication, a Verify error occurs?
④ If JTAG lock can be released, can this error be detected by Verify in JTAG communication?
During JTAG writing, can this problem occur due to the influence of power supply or noise of the writer?
Is it possible that Verify error does not occur and JTAG lock is applied even if an incorrect value is written?
Best Regards,
Ito




