MSP430FR5964: Setting up HFXT2 for External Clock Oscillator

I have it working now, the errors were:

 - The HFFREQ select bits must be set PRIOR to entering bypass mode (Table 3-1 Family Users Guide SLAU367P).
   -- " In addition, these bits should be configured properly before use of HFXT in either crystal or bypass modes of operation"

 - The alternate function pins for HFXIN and HFXOUT must be set for it to take effect.
   -- Section 3.2.3:
       "However, HFXT remains disabled until the ports shared with HFXT are configured for HFXT operation. The configuration of the shared I/O is determined by the PSEL bit associated with HFXIN and the HFXTBYPASS bit. Setting the PSEL bit causes the HFXIN and HFXOUT ports to be configured for HFXT operation."

 - Finally the HFXTOFFG must be cleared and then the interrupt flag OFIFG must be cleared in that order.

I guess the moral of the story is R.F.M.!

I've posted the code that is working below in case anyone else stumbles on this:

// ****************************************************************************************************************

// ************************************************************************
// CAUTION: Order May Matter!!!
// If making changes test, test, test that MCLK stays with XT2
// ************************************************************************
// Send MCLK out pin 68 for diagnostics
P5DIR |= BIT7;
P5SEL0 |= BIT7;
P5SEL1 |= BIT7;

// Must write to Clock Source Key before any other registers can be written
CSCTL0 = CSKEY;
// MCLK, SMCLK, ACLK all divide by 1
CSCTL3 = DIVM__1 | DIVS__1 | DIVA__1;
// Turn off LFEXT, HFFREQ = 8-16MHz (running at 10MHz)
// Must be set before going to bypass mode (See table 3-1 Note in family user guide SLAU367P
CSCTL4 = LFXTOFF_1 | HFFREQ_2;

// Bypass 3.3V Clock Oscillator used.
CSCTL4 |= HFXTBYPASS;

PJSEL0 |= BIT6 | BIT7;

// MCLK = HF EXT, SMCLK = HF EXT, ACLK = VLO INT
CSCTL2 = SELM__HFXTCLK | SELS__HFXTCLK | SELA__VLOCLK;

  // Clear HFXT Flag and interrupt, order matters
CSCTL5 &= ~(HFXTOFFG);
SFRIFG1 &= ~OFIFG;

// Wait "some time" for XT2 to become clock source
// Empirically testing shows loop iterations between 100-150
// Otherwise move on with defaults and let clock monitor task,
// gsMspClkRecoverXT1(), try to correct it
static volatile uint16_t _xt2FailCnt = 0;
_xt2FailCnt = 0;
do
{
_xt2FailCnt++;
// Clear HFXT Flag and interrupt, order matters
CSCTL5 &= ~(HFXTOFFG);
SFRIFG1 &= ~OFIFG;
// Test XT2 fault flag and loop iterations
} while ((CSCTL5 & HFXTOFFG) && (_xt2FailCnt < 1000));

_xt2FailCnt = _xt2FailCnt;