MSP430F5528 Pin capacitance tolerance

Bryan,

Happy New Year! I'm moving this post to our MSP430 forum for you to get help with your questions.

Blake

Here is an additional on the layout of the MSP430F5528IZQE.   We are considering grounding unused Px and PJ pins on the MSP430.  There is some concern that leaving them open may increase EMI susceptibility to very high fields (200-500V/m).   The documentation clearly indicates they should be OPEN, but this may be a special use case and for our design tying them to GND my be more appropriate.

Thank you,

Bryan Busacco

The recommendation is for minimizing power consumption. A grounded pin may introduce some leakage currents from the port input driver, and cause (relatively) high current when the pins pullup resistors are activated or (worse) the pin is switched to high output.

Leaving the pins unconnected, but switching them to low output, however, avoids any unwanted currents.

In our application, the concern for the MSP430F5528IZQE is that leaving them open may increase EMI susceptibility to very high fields (200-500V/m). If we are unconcerned about additional current drain, are cautious not to change the state of the pin to high output via software ( certainly bad ), will this limit susceptibility to the high EMI fields? Or do you suggest that even in this application we leave the pins open?

Thank you,

Bryan Busacco

Bryan,

I see that you're concerned about EMI/ESD protecting your pins here.

The reason we recommend leaving it open is because they are generic GPIO pins. Ultimately, for unused pins, they should be tied to OUTPUT low in software which essentially GNDs the pins internally.

I wouldn't recommend grounding it directly but maybe you could try putting a small resistive value in series to GND. This case you won't accidentally blow out your GPIO pin if you accidentally set it to OUTPUT high in your software. And you can still set it to OUTPUT Low in software even with the series resistor.

Regards,

William

Good answer on grounding unused pins, thank you,

Back to my original question of Cap Tolerance. Verbally I heard 10% is acceptable, Can we use 20% to save on board space? The 20% caps are in a smaller package and we are very tight in board space.

Original question:

Bryan,

As far as capacitance tolerances goes, there is an important ratio to follow in the datasheet (CDVCC/CVCORE ratio of 10). You should be ok if this value is followed for the Vcore. As a general rule, I would recommend a tighter capacitor tolerance if possible as these are important caps for stable Vcore voltages during powering up and operation. In our target board designs, we have been using +/-10%.

Looking around on Digikey, it looks like the smallest cap size with this tolerance is 0402.

Regards,

William G.

The only realyl important capacitance is the one on VCore. It mus tfit the internal core voltage generator. if it is too small, cor evoltage will oscillate, if it is too high, it may overload the generator, especially when switchign core voltages. The capacitance on VCC should be at least 10 times the one on VCore, so a 22µ capacitor with +20-80% would be as fine as any smaller one with tighter tolerances, as long as it stays in the range of 4.7µ or above. Vor VUSB, I cannot tell. I guess it should be in the USB specification and independent of the MSP. For V1.8 I don't know at all. I guess it is a minimum, required to keep the regulator stable. So a larger one won't hurt. It surely depends on the load too.