clock frequency testing

Hmm, I'd assume the lowest input frequency is 0Hz, as -1Hz is obviously impossible. Usually you want to know the highest frequency your application can still handle.
However, the constraints can usually be determined by a little bit of math (and of course knowing the application).
On FPGA, the test IMHO wants to determine the lowest clock needed to let the FPGA perform its task properly.

This would equal in changing the XT2 frequency (or rathe rMCLK frequency) ot determine how fast MCLK must be to handle a certain application.

However, this is not very 'telling' since the execution depends not only on the code, but also on the compiler and its version, the compiler settings, and perhaps a number of other parameter too.
If you really want this test, you can write code that will 1) output MCLK or SMCLK to a port pin 2) drive MCLK(+SMCLK) from DCO and 3) successively lower DCO frequency until the software won't work anymore (e.g. detect overruns/underruns etc.). The (S)MCLK output frequency on the pin is then the highest frequency on which it doesn't work anymore.
But of course, metering changes the data: your additional code for changing the DCO and checking the results will negatively affect performance.
In any case, it heavily depends on your application.