Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
I am trying to read the results of the 12-bit ADC via DMA on an MSPM0 device.
The ADC is triggered by a Timer0 zero-event, which occurs every second (Timer Period = 1000 ms).
On each trigger, the ADC performs a non-repeated sequence-of-channels conversion across 3 ADC channels (configured MEM0, MEM1, MEM2).
Once the sequence completes, the ADC asserts the MEM2_RESULT_LOADED interrupt. This should then trigger the DMA, which is configured to transfer the results from the ADC MEMx registers into an array.
The problem:
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The transfer works only the very first time the Timer hits zero.
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Every subsequent DMA transfer always contains the same first set of values, even when the physical input signals change (e.g., channels tied to GND).
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If I disable DMA and instead use the ADC interrupt handler to manually read the MEMx results, the values are updated correctly for every trigger.
What I’ve checked / observations:
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ADC sequence itself is working and producing new results (verified through ISR).
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The DMA channel is armed and interrupts fire as expected (DMA_DONE occurs).
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However, the destination buffer is never updated with fresh conversions after the first trigger.
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Buffer is a 32-bit array, DMA configured for half-word transfers (possible width mismatch?).
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Source increment is currently enabled (might be wrong, since all results come from fixed ADC MEM registers).
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DMA is initialized after the ADC is enabled — could ordering of ADC enable vs. DMA setup be relevant?
So it seems to be a configuration mismatch between ADC12 DMA triggering and the DMA channel setup (width, increment, init sequence) rather than an ADC problem.
Could you please confirm the expected configuration of DMA for multi-channel ADC sequences (e.g. srcIncrement, transfer width, init order)?
