What I want to do:
There is a external chip with a parallel interface ( 8 or 16 bits) and a strobe-clock. Each time the strobe-clock line from this chip goes low a new byte at the output port of this chip is valid.
Examples for this are fast ADC-chips or camera chips. E.g. see page 13 in this pdf:
http://www.sparkfun.com/datasheets/Sensors/Imaging/TCM8240MD_E150405_REV13.pdf
DCLK is the strobe clock I mentioned above, and there is a VBLK and HBLK signal to indicate the start of the stream. Does it make sense to interface a 1.3MPix camera chip - with 10MBytes for one raw picture - to the MSP430 wtih 16kBytes of RAM? Yes! I only need one line from the sensor (e.g. for bar code reader), and the TCM8240 is quite cheap.
How to do it using DMA:
I want to use a F5438A and its DMA capabilities to get the byte stream into the RAM of the MSP430. I will tie DCLK, VBLK and HBLK together using a NAND and feed this to P2.7 (DMAE0 this is DMATrigger31 signal). The parallel bus (D0-D7) is connected to a MSP430 port - e.g. P6. DCLK is asynchronous to MCLK. According to the datasheet the MSP430 needs 4 MCLK's to get a byte from the port to RAM after the DMA trigger signal has been activated.
The question:
When is the byte at input port P6 read? How long has the byte at P6 to be stable? In which of the 4 MCLK's is it read? I see no timing diagram in the datasheet.
My assumptions - after reading the manuals - are:
1st cycle: synchronise (finish the last command of the CPU)
2nd cycle: read P6
3rd cycle: write to RAM
4th cycle: synchronise
Is this ok? I think it is a good idea to put a latch in front to P6. With 24MHz MCLK the MSP430 should be able to handle a 6MHz DCLK.
Is there a better way to get a external clocked byte stream into RAM? Maybe it is better to try to get the external strobe clk synchonous to MCLK and use burst mode and just 2 MCLK cycles per byte. Hmm are there any application notes or examples available somewhere?
Thx
Matthias