What is MSP430F5XXX SMCLK default frequency at Power on?
I read datasheet of MSP430F5xxx (SLAU208J.PDF).http://www.ti.com/lit/ug/slau208j/slau208j.pdf
Page 382
NOTE: Watchdog timer powers up active.
After a PUC, the WDT_A module is automatically configured in the watchdog mode with an
initial ~32-ms reset interval using the SMCLK. The user must setup or halt the WDT_A prior
to the expiration of the initial reset interval.
Page 136
SELS Bits 6-4 Selects the SMCLK source
The SELS defualt is 100 DCOCLKDIV
Page 135
SELREF Bits 6-4 FLL reference select. These bits select the FLL reference clock source.
The SELREF defulat is 000 XT1CLK
My system have on external osc, only use REFO (32768Hz) to generate 16Mhz.
When mcu boot, if I don't nothing(dont initialize register),don't disable watchdog or reset watchdog,would happen watchdoc time out reset ?????
According the default value (The SELS defualt is 100 DCOCLKDIV.The SELREF defulat is 000 XT1CLK)
I have on external osc, the XT1CLK have no signal.
Power on,SMCLK have on signal,the watchdog would not work.
The system doesn't happen watchdog time out reset, Right????