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LP-MSPM0G3507: Order of I2C Target Initialization Steps Differs from those in the TRM

Michael Valentino-Manno
Prodigy 70 points
Part Number: LP-MSPM0G3507
Other Parts Discussed in Thread: MSPM0G3507, , SYSCONFIG

Hello,

I have a customer who is currently using a LP-MSPM0G3507 evaluation board and the provided i2c_target_rw_multibyte_fifo_interrupts_LP_MSPM0G3507_nortos_ticlang sample project to confirm the operation of the MSPM0G as an I2C target device. 

Their question is as follows:

  1. Why does the order of I2C initialization steps seen in the automatically generated ti_msp_dl_config.c file differ from the order listed in the TRMs section 24.2.4.2.1 Target Mode Operation I2C Target Initialization? Is there any guidance or more details on which steps listed in the TRM are required, optional, which have a fixed order and which can be done out of order and to what extent? 
    • e.g., the order of 3→4→5 is required, swapping steps 6 and 7 is fine, etc..  

 

Please let me know if you need any additional information.

Thank you,

Michael

 

  • 0
    TI__Prodigy 210 points

    Hey Michael,

    Generally, the way that Sysconfig sets the peripheral up is the reference for the correct steps to follow for the silicon, would you mind helping me understand the use-case where you're considering switching some of these steps?

    Steps 1-4 are important to do first, and generally it is best to go in the order of

    1.) pin-mux

    2.) assert reset

    3.) power

    4.) program target address

    5.) configure clock

    6.) configure other use-cases such as interrupts, FIFO, addressing mode, SMBus, etc.

    7.) after all configuration, enabling target mode and setting active in I2Cx.SCTR.

    Essentially, as long as the first few initialization steps are taken before configuring the other peripheral features, and only enabling target mode as the last step, it should work as intended.

    Best Regards,

    Tyler

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