MSP430FR6047: ADC capture lobe

Part Number: MSP430FR6047
Other Parts Discussed in Thread: TIDA-01486

Hi,

I’ve designed a system using the MSP450FR6047 with an externally controlled front end similar to the TIDA-01486 reference design.

My ADC capture looks like this, and I’m concerned about the downward-trending lobe in the waveform. What could this indicate? Does it suggest that I need larger DC-blocking capacitors in the receive path?

image.png

  • Hi,

    A downward-tilted lobe is a typical manifestation of baseline drift and bandwidth limitation caused by insufficient DC-blocking capacitance (or excessive ESR/ESL). You can try increasing the blocking capacitance at the receiver (and selecting high-precision, low-ESR ceramic capacitors) and checking the matching network.

    Thanks!

    Best Regards,
    Peter

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