• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 80 subscribers
  • Views 265 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430F5310: Watchdog Reset in Debug Mode

Ozawa Takeo
Prodigy 30 points

Part Number: MSP430F5310
Other Parts Discussed in Thread: MSP-FET

Hi,

I have a question about the watchdog timer behavior on the MSP430F5310.  
From my understanding, when a debug break occurs using the MSP-FET Flash Emulation Tool, the Embedded Emulation Module (EEM) halts certain internal CPU clocks. This also stops the clock feeding the watchdog timer, so normally a watchdog reset should not occur.  

However, in rare cases I have observed the watchdog timer triggering a reset even during such a debug break. The WDT-related register settings are identical to those during normal run-time operation.  

Could you please list possible conditions or scenarios under which the watchdog timer could still trigger a reset during debugging?

Thanks and regards,
Takeo

  • 0
    TI__Mastermind 24972 points

    Hi Ozawa,

    The only way the device should trigger a watchdog reset is if the Watchdog is not feed. Can you describe when exactly during a debug break it happens? Things like what happens before the hardware break happens? 

    Best Regards,

    Diego Abad

  • 0
    TI__Expert 8671 points

    Hi Takeo,

    You may observe this behavior in some cases, such as:

    • WDT sourced from an external oscillator
    • Timing of break
    • EEM may not be configured to halt clock

    Most likely this will be the result of the clock that is configured to be used by the WDT.

    This document is a good reference for the EEM: Advanced Debugging Using the Enhanced Emulation Module (EEM) With CCS 

    Best,

    Owen

  • 0 in reply to Owen Li
    Prodigy 30 points

    Hi Owen,

    Thank you for your response.
    Could you please clarify what ‘Timing of break’ specifically means in this context? I’m sorry for not fully understanding, but I would greatly appreciate it if you could explain the exact conditions involved.

    Best regards,
    Takeo

  • 0 in reply to Ozawa Takeo
    TI__Expert 8671 points

    Hi Takeo,

    Sorry for the confusion. By "timing of break" I mean the timing of stopping/halting the debug session. If this occurs close to the end of the period of the WDT, then there may be some instances where the WDT issues a reset. The clock may run for about 1-4 clocks before halting upon a debug break.

    Hope this answers your question. Feel free to follow up with any other questions you may have.

    Best,

    Owen

**Attention** This is a public forum