MSP430FR2111: Please tell me how to communicate serially using UART.

Thank you to everyone at the E2E Forum for your help.

I'm currently developing a system that uses the Texas Instruments MSP430FR2111 MCU.

The system sends measured values ​​to an external PC about once a day, using UART as the communication method.

I created source code for port initialization and data transmission, and am attempting to receive data using a PC terminal application via the FT232RL, but for some reason, when P1.6 (Rxd) is connected to the FT232RL's Txd, data cannot be sent from P1.7 (Txd).

I'm plagued by this mysterious phenomenon: if I disconnect the wire connecting P1.6 (Rxd) to the FT232RL's Txd, data can be sent from P1.7 (Txd).

I have multiple FT232RLs, so I tried several, but I got the same result with each.
I am attaching the current source code, and although I apologize for bothering you during your busy schedule, I would appreciate it if you could tell me how to solve the problem.
Thank you in advance.

#include <msp430.h>
#include <stdint.h> 

#pragma DATA_SECTION(accumulated_distance, ".myFRAM")
volatile uint32_t accumulated_distance;

#pragma DATA_SECTION(magic_flag, ".myFRAM")
volatile uint32_t magic_flag;

#define MAGIC_INITIALIZED   0xFFFFFFF0      // 2025.12.03
#define SMCLK_FREQ_HZ       1000000UL       // 2025.12.09
#define UART_BRW_VALUE      104
#define UART_MCTLW_VALUE    (UCOS16 | (2 << 4) | (0 << 8))

volatile uint8_t inc_flag = 0;

__interrupt void Port_1(void);

void uart_putc(char c);
void uart_puts(const char *s);

#define MCLK_FREQ_MHZ 1                     // MCLK = 1MHz

int main(void) {
    WDTCTL = WDTPW | WDTHOLD;               // Stop watchdog timer
    SYSCFG0 = FRWPPW;                       // 

    __bis_SR_register(SCG0);                // Disable FLL
    CSCTL3 = SELREF__REFOCLK;               // Set REFO as FLL reference source
    CSCTL1 = DCOFTRIMEN_0 | DCORSEL_0;      // DCO Range = 1MHz
    CSCTL2 = FLLD_0 + 30;                   // DCODIV = 1MHz
    __delay_cycles(3);
    __bic_SR_register(SCG0);                // Enable FLL
    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                               // default DCODIV as MCLK and SMCLK source

    //
    // P1.0 / A0
    P1SEL0 |= BIT0; P1SEL1 |= BIT0;

    // P1.1 / A1
    P1DIR |= BIT1;

    // P1.3 / A3
    P1SEL0 &= ~BIT3; P1SEL1 &= ~BIT3;   //
    P1DIR &= ~BIT3;                     //
    P1IES |= BIT3;                      //
    P1IFG &= ~BIT3;                     //
    P1IE |= BIT3;                       //

    // P1.4 / A4
    P1SEL0 &= ~BIT4; P1SEL1 &= ~BIT4;   //
    P1DIR |= BIT4;                      //
    P1OUT &= ~BIT4;                     //

    // P1.5 / A5
    P1SEL0 &= ~BIT5; P1SEL1 &= ~BIT5;   //
    P1DIR |= BIT5;                      //
    P1OUT &= ~BIT5;                     //

    // P2.0
    P2SEL0 &= ~BIT0; P2SEL1 &= ~BIT0;   //
    P2DIR  |= BIT0;                     //
    P2OUT  |= BIT0;                     //

    // P2.1
    P2SEL0 &= ~BIT1; P2SEL1 &= ~BIT1;   //
    P2DIR &= ~BIT1;                     //

    // UART
    // P1.6 = UCA0RXD, P1.7 = UCA0TXD
    // 1) stop eUSCI_A
    
    //----------------------------------------------------------
    // (1) RXD (P1.6)
    //----------------------------------------------------------
    P1DIR &= ~BIT6;      // RXD input
    P1OUT |= BIT6;       // pull-up
    P1REN |= BIT6;       // enable pull-up

    //
    __delay_cycles(200000);   // 200ms @1MHz

    //----------------------------------------------------------
    // (2) Function change
    //----------------------------------------------------------
    P1REN &= ~BIT6;            //
    P1SEL0 |=  BIT6 | BIT7;    //
    P1SEL1 &= ~(BIT6 | BIT7);

    //----------------------------------------------------------
    // (3) DIR
    //----------------------------------------------------------
    P1DIR &= ~BIT6;     //
    P1DIR |=  BIT7;     //

    //----------------------------------------------------------
    // (4)
    //----------------------------------------------------------
    UCA0CTLW0  =  UCSWRST;        //
    UCA0CTLW0 |=  UCSSEL__SMCLK;  // SMCLK = 1MHz

    // 9600bps @ 1MHz
    UCA0BR0 = 104;
    UCA0BR1 = 0;
    UCA0MCTLW = 0;                //

    UCA0CTLW0 &= ~UCSWRST;        // UART start

    // UCA0IE |= UCRXIE;                //

    // ADC
    ADCCTL0 &= ~ADCENC;                 //
    ADCCTL1 |= ADCSHP | ADCSSEL_2;      //
    ADCCTL2 |= ADCRES_2;                //

    ADCMCTL0 |= ADCINCH_0;              //

    ADCCTL0 |= ADCON;                   //
    ADCIE |= ADCIE0;                    //
    
    PM5CTL0 &= ~LOCKLPM5;                   // Disable the GPIO power-on default high-impedance mode
                                            // to activate previously configured port settings

    // Check if this is first-ever run
    if (magic_flag != MAGIC_INITIALIZED){
        accumulated_distance = 0;           // Initialize on first run only
        magic_flag = MAGIC_INITIALIZED;
    }

    __delay_cycles(500000);

// Example
    uart_puts("U");

    while(1)							//
    {
        __low_power_mode_3();           //
        //
        if (inc_flag){
            accumulated_distance++;
            inc_flag = 0;
        }
    }
}

void uart_putc(char c) {
    while (! (UCA0IFG & UCTXIFG));      //
    UCA0TXBUF = c;                      // send
}

void uart_puts(const char *s){
    while (*s){
        uart_putc(*s++);
    }
}

// Port 1.x interrupt service routine
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{    
   if (P1IFG & BIT3){                   //
        inc_flag = 1;                   //
        P1IFG &= ~BIT3;                 //
        __bic_SR_register_on_exit(LPM3_bits);
    }
}