Part Number: MSPM0G1507
We are defining a peripheral (slave) communication protocol that works over both I²C and SPI so the same register access implementation can be used for both interfaces. We are currently using the following protocol for SPI and are able to achieve ~4MHz while the MCU was operating at 80 MHz:
SPI Case:
Byte 1: CMD - Command (read or write)
Byte 2: ADDR - Register address
Byte 3: STALL - Stall Byte
Byte 4+: Variable count depending on transaction
- Single Byte: Single register access
- Multiple Bytes: block access with address automatically incremented for each next byte
Some questions we have:
1) It seems like the DL_SPI_isBusy() function sometimes returns incorrect status about the state of the SPI machine, especially when it happens to be called around the boundaries of the reception transfers with FIFO empty. Do you have any examples / guidance / documentation we should use to better understand the limitations of this function?
2) While writing the MCU will return arbitrary data (i.e. the empty FIFO previous contents). Similarly, while reading the MCU will return arbitrary data for the CMD, ADDR, and STALL bytes. Is there any way to clear the FIFO or return a known value? If not, that is ok, just not as ideal.
3) Do you have any performance data on your SPI peripheral implementations? We wanted to understand if 4MHz was the upper limit or if there were ways to increase performance?
