Part Number: MSP430G2553
Why is the MSP430 clocking after the CS goes high again?
This is my configuration:
UCB0CTL1 |= UCSWRST; // Put in reset
UCB0CTL0 |= UCMST + UCSYNC + UCCKPH + UCMSB; // SPI Master, Sync, MSB
UCB0CTL1 |= UCSSEL_3; // SMCLK
UCB0BR0 = 16; // SPI Speed (SMCLK/2)
UCB0BR1 = 0;
IFG2 &= ~UCB0TXIFG;
IFG2 &= ~UCB0RXIFG;
UCB0CTL1 &= ~UCSWRST; // Release reset
This is how I transmit:
P2OUT &= ~BIT5; // Clear Chip Select (activate)
while (!(IFG2 & UCA0TXIFG)); // Wait for TX buffer
UCA0TXBUF = data; // Send data
while (!(IFG2 & UCA0RXIFG)); // Wait for RX complete
return UCA0RXBUF; // Return received data
P2OUT |= BIT5; // Set Chip Select (deactivate)
