MSPM0G3507: TIMA Deadband Behavior when RISEDELAY exceeds PWM cycle in center-aligned mode

Michael V

Intellectual 566 points

Part Number: MSPM0G3507

Hi,

I have a question regarding the behavior of the TIMA module in the MSPM0G series when using deadband insertion.

Configuration:

Device: MSPM0G3507
Timer: TIMA
Mode: Center-aligned PWM
Complementary output enabled
Mode 1

Question:

In this configuration, CCP0N output edges are generated based on CCP0 edges with additional delay defined by RISEDELAY / FALLDELAY.

What happens when RISEDELAY is set to a value that effectively exceeds the remaining time within the current PWM cycle, such that the delayed edge would correspond to a timing point in the previous cycle (e.g., equivalent to the down-count position of the previous cycle)? Is this an accepted usecase?

Specifically:

Is the delayed output edge
- suppressed (masked) until that timing point, or
- simply delayed and allowed to cross into the next cycle?
If the delayed edge overlaps with a new compare event in the next cycle,
- does the hardware discard the previous delayed event,
- or is there any form of event queuing or priority handling?

From the TRM, deadband appears to be implemented as a delay relative to compare events, but the behavior when the delay exceeds the PWM period (or crosses cycle boundaries) is not clearly defined.

I have attached a conceptual waveform diagram to illustrate the scenario I am considering, where the orange arrow shows RISEDELAY being long enough to extend into the previous cycle.