MSPM0G3519: ULPCLK changing during ADC conversion when operating at less than 32 MHz

Hi Stephen,

Could you please check whether you have below configuration in your program?

• Configure SYSOSC frequency as 4MHz: DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_4M);
  

Hi Pengfei,

Thanks for your feedback. I checked the settings and they are as you have suggested. BLOCKASYNCALL=1, USE4MHZSTOP=1, FREQ=1 which is 4 MHz.

SYSOSCCFG:00010101 MCLKCFG:00401000 PMODECFG:00000000 SCR:00000004
STOP1 Temp : 20 C

The processor is running at 4MHz before the ADC conversion is started. This is confirmed by the CLK_OUT. The clock goes back to 4MHz during STOP1.

If I don't go into STOP1 and loop waiting for the conversion to complete the clock remains at 32 MHz the entire conversion time, and only switches back to 4 MHz at the end. If I read "Common ADC Use Case" at the bottom of page 1132 of the reference guide, I see that if the trigger occurs during RUN, which is in my case, the conversion should run without changing SYSOSC frequency. I'm puzzled.

Stephen

Hi Stephen,

I see from the TRM Common ADC Use Cases chapter that the SYSOSC will be forced to BASE if MCU is awaked from STOP1 mode. I'm not sure could you please share your example which could reproduce the frequency switching sequence you mentioned, so that I could also test and analyze from my side?

Claude helped me isolate some test code. See attached. Compiles in IAR. Runs on the MSPm0G3519 Eval board. Connect a probe to PB28 to trigger and PA7 for the clock.

#define USE_STOP1_WAIT  1 // set to 1 or 0 to enter STOP1 mode or not.

I do note that the debugger can change the clock when connected and active. 

Let me know if I can help with more info.TEST_ADC.zip

Hi Stephen,

I could see what your descripted also from my test. Let me check internally about it. Thanks.

Thanks. Looking forward to hearing the outcome. 

I think the Uart can cause a similar bump in frequency. 

Hi Stephen,

As I checked internally, by design, the SYSOSC clock will always get enabled (if disabled) and switch to 32MHz whenever an ADC conversion request is received. This will happen even if BLOCKASYNCALL is 1.

We plan to modify the corresponding description in Technical Reference Manual about SYSOSC frequency behavior during ADC conversion, and sorry for the inconvenience of it.

As for UART, I think UART transmission will not cause the same issue for SYSOSC from my test if Async Fast Clock Request is disabled. 

Hi Pengfei,

Thanks. That does make the ADC sampling and conversion time difficult to predict because the clock is changing. The only reliable way is to set SYSOSC at 32 MHz when using the ADC. This has power implications. I would expect the original intension of only enabling or changing SYSOSC when it is off, and a conversion is triggered, is the way it should be.

Hi Stephen,

As it is a fact that SYSOSC will always to be triggered to 32MHz during ADC conversion, do you think it is acceptable to manually switch SYSOSC to 32MHz before ADC conversion? As we have no way to avoid SYSOSC switching to 32MHz during ADC conversion, by manually switch SYSOSC frequency, the sampling time becomes predictable.