MSPM33C321A: UART DMA interface misses last bytes when configured for variable length reception

Hi Rajeshwary,

The RX TIMEOUT event should be treated as an indication that no additional UART character was received within the configured timeout. It should not be treated as a guarantee that all pending DMA writes to the receive buffer have completed. If RX TIMEOUT is selected as the DMA trigger, then the timeout event itself can be the event that initiates the DMA request for the remaining byte/data in the UART receive path. Therefore, software may observe the timeout condition before the final DMA write is visible in memory.

For variable-length UART reception, we recommend using the normal UART RX DMA trigger to move incoming bytes into the DMA buffer, and using RX TIMEOUT as an end-of-packet indication. On timeout, the application should stop/synchronize the DMA channel, read the remaining DMA transfer count, calculate the received length, and then process the buffer.

In other words, RX TIMEOUT is useful to detect the end of a variable-length frame, but it should not be used alone as proof that the DMA buffer is already complete. Also, FIFO-empty status alone is not sufficient to confirm the data is already committed to SRAM, because the DMA may have already removed the byte from the FIFO while the memory write/count update is still pending.

Please also ensure the application is not disabling the DMA channel or clearing the timeout/DMA event before the timeout-triggered DMA request has completed. If the ISR disables DMA immediately on RX TIMEOUT, it may race with the final DMA transfer.

We would suggest testing with UART RX DMA trigger enabled for normal reception and RX TIMEOUT interrupt used only to delimit the packet. The MSPM33 SDK also includes UART RX multibyte FIFO DMA interrupt examples that can be used as a starting point for DMA-based UART reception.

Hi Jojo,

Below is the code patch for reading DMA transfer size in DL_UART_INTERRUPT_RX_TIMEOUT_ERROR  interrupt

Regards,

Rajeshwary

Hi Rajeshwary,

Thanks for the update and the SysConfig screenshot. The new approach of using UART RX interrupt as the DMA RX trigger and RX TIMEOUT as the frame boundary is the right direction.

A few things to check:

1. In single-transfer DMA mode, the DMA transfer size of 64 means 64 UART RX trigger events are required before the DMA block is complete. If the actual received packet is 5 bytes, the expected remaining count would be 59, not 5. The received length would then be 64 - 59 = 5 bytes.

2. Please read the DMA transfer size before disabling the DMA channel. In the code patch, the DMA channel is disabled before calling DL_DMA_getTransferSize(). Disabling the DMA channel may affect the live channel state, so the count should be captured first.

3. The screenshot shows “Configure Transfer Size” unchecked. If SysConfig is not setting the transfer size, please make sure the application calls DL_DMA_setTransferSize(DMA0, DMA0_CH1_CHAN_ID, 64) every time before enabling the DMA channel.

4. Please also confirm that the RX DMA destination address increments after each transfer. For UART RX DMA, the source address should remain unchanged at UART RXDATA, but the destination address must increment so each received byte is stored into the next buffer location.

As an alternative to using DL_DMA_getTransferSize(), we recommend reading the current DMA destination address at RX TIMEOUT and calculating the received length as:

rxLen = current DMA destination address - start address of RX buffer

This avoids ambiguity around reading the transfer-size register after the DMA channel is disabled or after DMA completion.

Recommended timeout handling order:

- Disable the UART RX DMA event to prevent new DMA requests
- Read the DMA destination address or transfer count
- Calculate rxLen
- Disable/re-arm the DMA channel for the next packet
- Re-enable UART RX DMA event

Hi Jojo,

I tried the with recommended timeout handling order as suggested with DMA RX trigger source as UART RX interrupt. Still, I always receive DL_DMA_getTransferSize() output as 0. I checked the DMA destination address in the RX Timeout as below

current DMA destination address = 0x3000800D

start address of RX buffer = 0x30007FCD

rxLen = 64.

Once I move my DMA trigger source to UART RX Timeout interrupt I always receive DL_DMA_getTransferSize() output as 4 and 

current DMA destination address = 0x30007FD1

start address of RX buffer = 0x30007FCD

rxLen = 4.

Have you tried the suggested solution? Can you provide me test code for it?

Looking for quick resolution of the issue.

Regards,

Rajeshwary