Part Number: MSPM0G3518-Q1
Te following is from the syscfg regarding the IWDT peripheral of G3519 MCU :-
The Independent Watchdog timer (IWDT) is part of the LFSS IP and is an SoC independent supervisor which monitors code execution and overall hang up scenarios of the SoC. Due to the nature of the LFSS IP, this WDT has its own system independent power and clock source. If the application software does not successfully reset the watchdog within the programmed time, the watchdog generates a POR reset to the SoC.
Under Basic Configuration users can:
- Configure the clock divider and frequency
- Configure IWDT period
- Enable IWDT to continue running when the CPU is halted for debug
- Enable lock function protection of WDT registers so they cannot be changed after initial configuration on accident by software or during an address transient error during an intentional write access
But the reset reason should be IWDT reset, why does syscfg says that the reset reason shall be POR if the countdown expires?
