• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 80 subscribers
  • Views 101 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSPM33C321A: DMA Ping-Pong with SPI

Keith Barkley
Guru 44155 points

Part Number: MSPM33C321A

Just how do I set up for Ping-Ponging from one buffer to the next and dma it out to SPI? I currently use a timer to send each buffer after a certain time - which might be how things end up - but I wanted to see if I could get it going as fast as possible.

The TRM simply says that the half-way buffer interrupt facilitates ping-ponging, but gives no details.

  • 0
    Guru 103245 points

    [I haven't done this, but no one else seems to be speaking up.]

    I don't see any provision for ping-pong per se (as seen in e.g. the Tiva uDMA). I suspect they have in mind using DMAPREIRQ (DMASZ=half) along with DMA completion (DMASZ=0) as a half-transfer mechanism. I.e. you run in Repeat Single, and each time you see a PREIRQ or completion, you quickquick load your new data into the half of the buffer that was just sent. The transmission speed determines the buffer size (i.e. deadline). I've done this on an MCU from [other guys] but not on the M33.

  • 0
    TI__Intellectual 2200 points

    Hey Keith,

    The timer approach is an open-loop guess at the SPI's drain rate. Instead, use the SPI TX DMA trigger as the channel's trigger source. Now the FIFO paces the DMA itself, that is, a frame shifts out, a slot opens, the DMA refills it. This makes it fast as possible. Since, SPI supports a TX FIFO threshold, you can tune how early the trigger asserts.

    For ping-pong, just as Brunce hinted on, one contiguous buffer of 2N, one repeat-capable FULL channel in repeated mode, source incrementing through the buffer, destination fixed at the SPI TX data register, DMAPREIRQ = half. So essentially, you have two interrupts per pass: PREIRQ at the midpoint means the DMA just finished the lower half and is now transmitting the upper half, while CPU refills the lower half. The completion interrupt, DMASZ=0, means it just finished the upper half so CPU can refill that one. Also, as you may know, you  never reprogram the channel since it's repeated mode. 

    Also, the TX FIFO is empty at boot, so the trigger condition is already true. A trigger that fires before the DMA is armed is simply lost according to the TRM in 7.2.5. Hence order matters, that is, configure with DMAEN=0 → pre-fill both halves → DMAEN=1 → then unmask the SPI TX trigger.

**Attention** This is a public forum